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Thu, 22 Oct 2020 08:08:26 -0700 (PDT) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:527:767:b750:2d3c]) by smtp.gmail.com with ESMTPSA id y6sm1233816ilj.59.2020.10.22.08.08.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2020 08:08:26 -0700 (PDT) From: Adam Ford To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/4] arm64: dts: imx8mn: add GPC node and power domains Date: Thu, 22 Oct 2020 10:08:06 -0500 Message-Id: <20201022150808.763082-4-aford173@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201022150808.763082-1-aford173@gmail.com> References: <20201022150808.763082-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201022_110828_916246_C66B8999 X-CRM114-Status: GOOD ( 12.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, devicetree@vger.kernel.org, Fabio Estevam , Andrey Smirnov , Adam Ford , Sascha Hauer , aford@beaconembedded.com, linux-kernel@vger.kernel.org, Rob Herring , NXP Linux Team , Pengutronix Kernel Team , Shawn Guo , l.stach@pengutronix.de Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds the DT nodes to describe the power domains available on the i.MX8MN. There are four power domains, but the displaymix and mipi power domains need a separate clock block controller which is also pending for 8MP and 8MM. Once the path for those is clear, Nano will need something similar, but the registers for Nano differ. For now, the dispmix and mipi are placeholders. Signed-off-by: Adam Ford diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 9b4baf7bdfb1..27733fbe87e9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -596,6 +596,55 @@ src: reset-controller@30390000 { interrupts = ; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mn-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_hsiomix: power-domain@0 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MN_CLK_USB_BUS>; + }; + + pgc_otg1: power-domain@1 { + #power-domain-cells = <0>; + reg = ; + power-domains = <&pgc_hsiomix>; + }; + + pgc_gpumix: power-domain@2 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_AHB>; + resets = <&src IMX8MQ_RESET_GPU_RESET>; + }; + + dispmix_pd: power-domain@3 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + }; + + mipi_pd: power-domain@4 { + #power-domain-cells = <0>; + reg = ; + power-domains = <&dispmix_pd>; + }; + }; + }; }; aips2: bus@30400000 {