@@ -63,3 +63,71 @@ flash@0,0 {
reg = <0x00 0x00 0x4000000>;
};
};
+
+&mailbox0_cluster0 {
+ interrupts = <436>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ interrupts = <432>;
+
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ status = "disabled";
+};
+
+&mailbox0_cluster3 {
+ status = "disabled";
+};
+
+&mailbox0_cluster4 {
+ status = "disabled";
+};
+
+&mailbox0_cluster5 {
+ status = "disabled";
+};
+
+&mailbox0_cluster6 {
+ status = "disabled";
+};
+
+&mailbox0_cluster7 {
+ status = "disabled";
+};
+
+&mailbox0_cluster8 {
+ status = "disabled";
+};
+
+&mailbox0_cluster9 {
+ status = "disabled";
+};
+
+&mailbox0_cluster10 {
+ status = "disabled";
+};
+
+&mailbox0_cluster11 {
+ status = "disabled";
+};
Add the sub-mailbox nodes that are used to communicate between MPU and various remote processors present in the J7200 SoCs to the J7200 common processor board. These include the R5F remote processors in the dual-R5F clusters in the MCU domain (MCU_R5FSS0) and the MAIN domain (MAIN_R5FSS0). These sub-mailbox nodes utilize the System Mailbox clusters 0 and 1. All the remaining mailbox clusters are currently not used on A72 core, and so are disabled. The nodes are added in the k3-j7200-som-p0.dtsi file to co-locate these alongside future reserved-memory nodes required for remoteprocs. The sub-mailbox nodes added match the hard-coded mailbox configuration used within the TI RTOS IPC software packages. A sub-mailbox node is added for each of the R5F cores to accommodate the R5F processor sub-systems running in Split mode. Only the sub-mailbox node for the first R5F core in each cluster is used in case of Lockstep mode for that R5F cluster. NOTE: The GIC_SPI interrupts to be used are dynamically allocated and managed by the System Firmware through the ti-sci-intr irqchip driver. So, only valid interrupts that are used by the sub-mailbox devices (each cluster's User 0 IRQ output) are enabled. This is done to minimize the number of NavSS Interrupt Router outputs utilized. Signed-off-by: Suman Anna <s-anna@ti.com> --- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 68 +++++++++++++++++++++ 1 file changed, 68 insertions(+)