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dmarc=none action=none header.from=nxp.com; Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) by HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.27; Tue, 27 Oct 2020 07:40:31 +0000 Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e]) by HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e%4]) with mapi id 15.20.3477.028; Tue, 27 Oct 2020 07:40:31 +0000 From: Zhiqiang Hou To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, leoyang.li@nxp.com, gustavo.pimentel@synopsys.com Subject: [PATCHv2 1/7] PCI: dwc: Fix a bug of the case dw_pci->ops is NULL Date: Tue, 27 Oct 2020 15:29:55 +0800 Message-Id: <20201027073001.41808-2-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> References: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> X-Originating-IP: [119.31.174.73] X-ClientProxiedBy: SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) To HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.73) by SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: hcm7Ul3kfTUBEhXGfVzaVLi8l6i8ncnbD2Vt7ONS7uUPPQiQ7Snw7h3D9UZdWGPQUyXproUxjxhk94qc+wss0nuM3JzfPcmu16UlPDMoBPwYk4+r1UFdq/z4C8oxtBUTZeKUn1K5FJ28dk/QEvGOXQOWijEdmMRZ3cGG4ue9jrgMaSVsBNvvR1rIdoJzxGo8AeCLbSktCtGQpIpDefSjildnDQ3J6kSvgaDREy86l+9C0UDh++JLpfnylodpMUAm8uUSaF9nkWF3KhsSw6wrueVvVddxNkCZj1l+MgnVOtXVEDiWTd1K1azbq5xnHRKH9ptYma18XFbjPq9HkBDPIurVVhVgQqZwoQXQkf99uCCA89eP+n9NA9v1Nthmyxa52dxi7YCUCuv97FyTPbECuM+R3blreBYwMiUqeRbRXa/ADm8zFmR/Hk8BdrzKirVmFoGb4sHRf+rFpq7dXe6lfCiJ20NR+ipZlgQLk4YFg3t/AJYCKBMLJMKG1RT66zQUqPbhWwjGVPb+YlpOYboOyT8vBzs90/SDvUuLacA4GD6dQiWf1LHdWRyi+KiFHKghd5B0PpuD1z9q8H+QoRbn7pW9uH9thmYHRas0Qie7X/59HbGEwCkItVurbcILaIg9lXo23F4QspkmzOsAqr5Wxw== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6eaf557c-4359-4ed3-5895-08d87a4b7340 X-MS-Exchange-CrossTenant-AuthSource: HE1PR0402MB3371.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2020 07:39:35.1615 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: AcmWZNwpZLAw2uXMSlnPGOh3RIzeEEp0K9BoJExg7cT92+/5qrWZhEwVWO3k3u72px87zm4SzSPQ+IIokCHNtQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0402MB3371 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201027_034122_084102_6902D726 X-CRM114-Status: GOOD ( 14.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: minghuan.Lian@nxp.com, Hou Zhiqiang , mingkai.hu@nxp.com, roy.zang@nxp.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Hou Zhiqiang The dw_pci->ops may be a NULL, and fix it by adding one more check. Signed-off-by: Hou Zhiqiang Reviewed-by: Rob Herring Acked-by: Gustavo Pimentel --- V2: - Rebased the patch against the latest code. drivers/pci/controller/dwc/pcie-designware.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index c2dea8fc97c8..7a5024450c4d 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -141,7 +141,7 @@ u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size) int ret; u32 val; - if (pci->ops->read_dbi) + if (pci->ops && pci->ops->read_dbi) return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); ret = dw_pcie_read(pci->dbi_base + reg, size, &val); @@ -156,7 +156,7 @@ void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) { int ret; - if (pci->ops->write_dbi) { + if (pci->ops && pci->ops->write_dbi) { pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); return; } @@ -171,7 +171,7 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) { int ret; - if (pci->ops->write_dbi2) { + if (pci->ops && pci->ops->write_dbi2) { pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); return; } @@ -186,7 +186,7 @@ static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg) int ret; u32 val; - if (pci->ops->read_dbi) + if (pci->ops && pci->ops->read_dbi) return pci->ops->read_dbi(pci, pci->atu_base, reg, 4); ret = dw_pcie_read(pci->atu_base + reg, 4, &val); @@ -200,7 +200,7 @@ static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val) { int ret; - if (pci->ops->write_dbi) { + if (pci->ops && pci->ops->write_dbi) { pci->ops->write_dbi(pci, pci->atu_base, reg, 4, val); return; } @@ -271,7 +271,7 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, { u32 retries, val; - if (pci->ops->cpu_addr_fixup) + if (pci->ops && pci->ops->cpu_addr_fixup) cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); if (pci->iatu_unroll_enabled) { @@ -479,7 +479,7 @@ int dw_pcie_link_up(struct dw_pcie *pci) { u32 val; - if (pci->ops->link_up) + if (pci->ops && pci->ops->link_up) return pci->ops->link_up(pci); val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);