From patchwork Tue Oct 27 17:26:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Elisei X-Patchwork-Id: 11861153 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 464D0C55179 for ; Tue, 27 Oct 2020 17:27:11 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C964921D24 for ; Tue, 27 Oct 2020 17:27:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="2dfC5nil" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C964921D24 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=myIE9L6OhoFAHvi98pw8QOcdC7ywpO5aYpwNnFl+h/w=; b=2dfC5nilhzZ4a65wJaJiO9cWp otBm4x15/CaXluPwA76wfuTYt5QjznXYxpHOoNIVkobMO0PRvy6rk3uDQhmAwW2UmUGHVvm1vhdlg riu6vRKKLAnDyv+fQMmGVxRPd37Bjv/ysf6zx6zGnO2dUQ3j6vXPFlZ7v2GH+2gEK7HRpJhHRlQzF RrJkofoVrYsu39lCSYZHy8oZMh1heQmRc2OKI4vU3LDfoLCY769xvFYVXRCqA0892XdewaStrhIx9 +VClP5AmCFlcwTrrbwR5h8HLio8YFzwPqsYhLXa4CuJ19p9MM02rkjKMlC+vuVG5LDCi4X8Ycc0oB tLFyamRLQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXSk1-0004tG-Fg; Tue, 27 Oct 2020 17:26:37 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXSjj-0004nX-AF for linux-arm-kernel@lists.infradead.org; Tue, 27 Oct 2020 17:26:20 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9901115AD; Tue, 27 Oct 2020 10:26:18 -0700 (PDT) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6EE093F719; Tue, 27 Oct 2020 10:26:17 -0700 (PDT) From: Alexandru Elisei To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu Subject: [RFC PATCH v3 03/16] KVM: arm64: Hide SPE from guests Date: Tue, 27 Oct 2020 17:26:52 +0000 Message-Id: <20201027172705.15181-4-alexandru.elisei@arm.com> X-Mailer: git-send-email 2.29.1 In-Reply-To: <20201027172705.15181-1-alexandru.elisei@arm.com> References: <20201027172705.15181-1-alexandru.elisei@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201027_132619_425965_E747A642 X-CRM114-Status: GOOD ( 14.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: maz@kernel.org, will@kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When SPE is not implemented, accesses to the SPE registers cause an undefined exception. KVM advertises the presence of SPE in the ID_AA64DFR0_EL1 register, but configures MDCR_EL2 to trap accesses to the registers and injects an undefined exception when that happens. The architecture doesn't allow trapping access to the PMBIDR_EL1 register, which means the guest will be able to read it even if SPE is not advertised in the ID register. However, since it's usually better for a read to unexpectedly succeed than to cause an exception, let's stop advertising the presence of SPE to guests to better match how KVM emulates the architecture. Signed-off-by: Alexandru Elisei --- arch/arm64/kvm/sys_regs.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d9117bc56237..aa776c006a2a 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -244,6 +244,12 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu, return true; } +static unsigned int spe_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *r) +{ + return REG_HIDDEN_GUEST | REG_HIDDEN_USER; +} + static bool access_actlr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -1143,6 +1149,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, val = cpuid_feature_cap_perfmon_field(val, ID_AA64DFR0_PMUVER_SHIFT, ID_AA64DFR0_PMUVER_8_1); + /* Don't advertise SPE to guests */ + val &= ~(0xfUL << ID_AA64DFR0_PMSVER_SHIFT); } else if (id == SYS_ID_DFR0_EL1) { /* Limit guests to PMUv3 for ARMv8.1 */ val = cpuid_feature_cap_perfmon_field(val, @@ -1590,6 +1598,17 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, + { SYS_DESC(SYS_PMSCR_EL1), .visibility = spe_visibility }, + { SYS_DESC(SYS_PMSICR_EL1), .visibility = spe_visibility }, + { SYS_DESC(SYS_PMSIRR_EL1), .visibility = spe_visibility }, + { SYS_DESC(SYS_PMSFCR_EL1), .visibility = spe_visibility }, + { SYS_DESC(SYS_PMSEVFR_EL1), .visibility = spe_visibility }, + { SYS_DESC(SYS_PMSLATFR_EL1), .visibility = spe_visibility }, + { SYS_DESC(SYS_PMSIDR_EL1), .visibility = spe_visibility }, + { SYS_DESC(SYS_PMBLIMITR_EL1), .visibility = spe_visibility }, + { SYS_DESC(SYS_PMBPTR_EL1), .visibility = spe_visibility }, + { SYS_DESC(SYS_PMBSR_EL1), .visibility = spe_visibility }, + { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },