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Mon, 09 Nov 2020 03:33:02 -0800 (PST) Received: from localhost ([2a01:4b00:8523:2d03:209d:10b7:c480:3e1f]) by smtp.gmail.com with ESMTPSA id t11sm12458783wmf.35.2020.11.09.03.33.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Nov 2020 03:33:01 -0800 (PST) From: David Brazdil To: kvmarm@lists.cs.columbia.edu Subject: [PATCH v1 11/24] kvm: arm64: Add SMC handler in nVHE EL2 Date: Mon, 9 Nov 2020 11:32:20 +0000 Message-Id: <20201109113233.9012-12-dbrazdil@google.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201109113233.9012-1-dbrazdil@google.com> References: <20201109113233.9012-1-dbrazdil@google.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201109_063304_498496_7B33013F X-CRM114-Status: GOOD ( 15.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , kernel-team@android.com, Lorenzo Pieralisi , Andrew Walbran , Suzuki K Poulose , Marc Zyngier , Quentin Perret , linux-kernel@vger.kernel.org, James Morse , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Tejun Heo , Dennis Zhou , Christoph Lameter , David Brazdil , Will Deacon , Julien Thierry , Andrew Scull Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add handler of host SMCs in KVM nVHE trap handler. Forward all SMCs to EL3 and propagate the result back to EL1. This is done in preparation for validating host SMCs in KVM nVHE protected mode. Signed-off-by: David Brazdil --- arch/arm64/kvm/hyp/nvhe/hyp-main.c | 35 ++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c index 19332c20fcde..8661bc7deaa9 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c @@ -106,6 +106,38 @@ static void handle_host_hcall(struct kvm_cpu_context *host_ctxt) host_ctxt->regs.regs[1] = ret; } +static void skip_host_instruction(void) +{ + write_sysreg_el2(read_sysreg_el2(SYS_ELR) + 4, SYS_ELR); +} + +static void forward_host_smc(struct kvm_cpu_context *host_ctxt) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_smc(host_ctxt->regs.regs[0], host_ctxt->regs.regs[1], + host_ctxt->regs.regs[2], host_ctxt->regs.regs[3], + host_ctxt->regs.regs[4], host_ctxt->regs.regs[5], + host_ctxt->regs.regs[6], host_ctxt->regs.regs[7], + &res); + host_ctxt->regs.regs[0] = res.a0; + host_ctxt->regs.regs[1] = res.a1; + host_ctxt->regs.regs[2] = res.a2; + host_ctxt->regs.regs[3] = res.a3; +} + +static void handle_host_smc(struct kvm_cpu_context *host_ctxt) +{ + /* + * Unlike HVC, the return address of an SMC is the instruction's PC. + * Move the return address past the instruction. + */ + skip_host_instruction(); + + /* Forward SMC not handled in EL2 to EL3. */ + forward_host_smc(host_ctxt); +} + void handle_trap(struct kvm_cpu_context *host_ctxt) { u64 esr = read_sysreg_el2(SYS_ESR); @@ -114,6 +146,9 @@ void handle_trap(struct kvm_cpu_context *host_ctxt) case ESR_ELx_EC_HVC64: handle_host_hcall(host_ctxt); break; + case ESR_ELx_EC_SMC64: + handle_host_smc(host_ctxt); + break; default: hyp_panic(); }