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Mon, 09 Nov 2020 10:11:07 -0800 (PST) Received: from localhost.localdomain ([2405:201:c809:c7a4:c0f0:b8ab:4687:594d]) by smtp.gmail.com with ESMTPSA id 136sm12027685pfa.132.2020.11.09.10.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2020 10:11:07 -0800 (PST) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Catalin Marinas , Will Deacon Subject: [PATCH 6/9] arm64: dts: rockchip: px30-engicam: Add BT support Date: Mon, 9 Nov 2020 23:40:14 +0530 Message-Id: <20201109181017.206834-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201109181017.206834-1-jagan@amarulasolutions.com> References: <20201109181017.206834-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201109_131111_444736_526A7653 X-CRM114-Status: GOOD ( 13.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Jagan Teki , Suniel Mahesh , Michael Trimarchi , linux-amarula , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suniel Mahesh Engicam PX30 carrier boards like EDIMM2.2 and C.TOUCH2.0 have an onboard Sterling-LWD Wifi/BT chip based on BCM43430 connected on the UART bus. UART bus on the design routed via USB to UART CP20x bridge. This bridge powered from 3V3 regualtor gpio. This patch adds BT enablement nodes for these respective boards. Signed-off-by: Michael Trimarchi Signed-off-by: Suniel Mahesh Signed-off-by: Jagan Teki --- .../arm64/boot/dts/rockchip/px30-engicam-common.dtsi | 12 ++++++++++++ .../boot/dts/rockchip/px30-engicam-ctouch2.dtsi | 10 ++++++++++ .../dts/rockchip/px30-engicam-px30-core-edimm2.2.dts | 10 ++++++++++ 3 files changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi index 92681ccf50f1..eb2be7893863 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi @@ -40,6 +40,18 @@ sdio_pwrseq: sdio-pwrseq { pinctrl-names = "default"; pinctrl-0 = <&wifi_enable_h>; }; + + vcc3v3_btreg: vcc3v3-btreg { + compatible = "regulator-gpio"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable_h>; + regulator-name = "btreg-gpio-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + states = <3300000 0x0>; + }; }; &sdio { diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi index d5708779c285..bf10a3d29fca 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi @@ -8,6 +8,12 @@ #include "px30-engicam-common.dtsi" &pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; @@ -18,3 +24,7 @@ wifi_enable_h: wifi-enable-h { &sdio_pwrseq { reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; }; + +&vcc3v3_btreg { + enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts index 913444548b59..d759478e1c84 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts @@ -21,6 +21,12 @@ chosen { }; &pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; @@ -31,3 +37,7 @@ wifi_enable_h: wifi-enable-h { &sdio_pwrseq { reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; }; + +&vcc3v3_btreg { + enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; +};