| Message ID | 20201123170132.17859-2-amelie.delaunay@st.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | STM32 USBPHYC PLL management rework | expand |
On Mon, 23 Nov 2020 18:01:27 +0100, Amelie Delaunay wrote: > PLL block requires to be powered with 1v1 and 1v8 supplies to catch ENABLE > signal. > Currently, supplies are managed through phy_ops .power_on/off, and PLL > activation/deactivation is managed through phy_ops .init/exit. > The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB > drivers dependent. > To ensure a good behavior of the PLL, supplies have to be managed at PLL > activation/deactivation. That means the supplies need to be put in usbphyc > parent node and not in phy children nodes. > > Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> > --- > Note that even with bindings change, it doesn't break the backward > compatibility: old device trees are still compatible, USB is still > functional. Device trees will be updated with this new bindings > when approved. > --- > .../bindings/phy/phy-stm32-usbphyc.yaml | 22 +++++++++---------- > 1 file changed, 10 insertions(+), 12 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml index 0ba61979b970..46df6786727a 100644 --- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml @@ -45,6 +45,12 @@ properties: "#size-cells": const: 0 + vdda1v1-supply: + description: regulator providing 1V1 power supply to the PLL block + + vdda1v8-supply: + description: regulator providing 1V8 power supply to the PLL block + #Required child nodes: patternProperties: @@ -61,12 +67,6 @@ patternProperties: phy-supply: description: regulator providing 3V3 power supply to the PHY. - vdda1v1-supply: - description: regulator providing 1V1 power supply to the PLL block - - vdda1v8-supply: - description: regulator providing 1V8 power supply to the PLL block - "#phy-cells": enum: [ 0x0, 0x1 ] @@ -90,8 +90,6 @@ patternProperties: required: - reg - phy-supply - - vdda1v1-supply - - vdda1v8-supply - "#phy-cells" additionalProperties: false @@ -102,6 +100,8 @@ required: - clocks - "#address-cells" - "#size-cells" + - vdda1v1-supply + - vdda1v8-supply - usb-phy@0 - usb-phy@1 @@ -116,22 +116,20 @@ examples: reg = <0x5a006000 0x1000>; clocks = <&rcc USBPHY_K>; resets = <&rcc USBPHY_R>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; #address-cells = <1>; #size-cells = <0>; usbphyc_port0: usb-phy@0 { reg = <0>; phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; #phy-cells = <0>; }; usbphyc_port1: usb-phy@1 { reg = <1>; phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; #phy-cells = <1>; }; };
PLL block requires to be powered with 1v1 and 1v8 supplies to catch ENABLE signal. Currently, supplies are managed through phy_ops .power_on/off, and PLL activation/deactivation is managed through phy_ops .init/exit. The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB drivers dependent. To ensure a good behavior of the PLL, supplies have to be managed at PLL activation/deactivation. That means the supplies need to be put in usbphyc parent node and not in phy children nodes. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> --- Note that even with bindings change, it doesn't break the backward compatibility: old device trees are still compatible, USB is still functional. Device trees will be updated with this new bindings when approved. --- .../bindings/phy/phy-stm32-usbphyc.yaml | 22 +++++++++---------- 1 file changed, 10 insertions(+), 12 deletions(-)