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[118.13.124.123]) by smtp.googlemail.com with ESMTPSA id a4sm41757578pjq.0.2020.11.30.05.10.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Nov 2020 05:10:57 -0800 (PST) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/9] dt-bindings: mstar: Add binding details for mstar, smpctrl Date: Mon, 30 Nov 2020 22:10:39 +0900 Message-Id: <20201130131047.2648960-2-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201130131047.2648960-1-daniel@0x0f.com> References: <20201130131047.2648960-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201130_081100_341095_025B9479 X-CRM114-Status: GOOD ( 16.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robh@kernel.org, daniel@0x0f.com, linux-kernel@vger.kernel.org, arnd@arndb.de, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds a YAML description of the smpctrl node needed by the platform code for the MStar/SigmaStar Armv7 SoCs to boot secondary cpus. Signed-off-by: Daniel Palmer --- .../bindings/arm/mstar/mstar,smpctrl.yaml | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml new file mode 100644 index 000000000000..a102287b5c88 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 thingy.jp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MStar/SigmaStar Armv7 SoC SMP control registers + +maintainers: + - Daniel Palmer + +description: | + MStar/SigmaStar's Armv7 SoCs that have more than one processor + have a region of registers that allow setting the boot address + and a magic number that allows secondary processors to leave + the loop they are parked in by the boot ROM. + +properties: + compatible: + items: + - const: mstar,smpctrl + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + smpctrl@204000 { + compatible = "mstar,smpctrl"; + reg = <0x204000 0x200>; + };