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[118.13.124.123]) by smtp.googlemail.com with ESMTPSA id a4sm41757578pjq.0.2020.11.30.05.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Nov 2020 05:11:05 -0800 (PST) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/9] ARM: mstar: Add infinity2m support Date: Mon, 30 Nov 2020 22:10:42 +0900 Message-Id: <20201130131047.2648960-5-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201130131047.2648960-1-daniel@0x0f.com> References: <20201130131047.2648960-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201130_081110_563354_B4136263 X-CRM114-Status: GOOD ( 18.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robh@kernel.org, daniel@0x0f.com, linux-kernel@vger.kernel.org, arnd@arndb.de, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The infinity2m series of chips are like the other Mstar/Sigmastar chips in that they have a Cortex A7 system with DDR memory integrated in a single package. The infinity2m chips are intended for recording the incoming streams from IP cameras. So instead of video encoders they have video decoders, instead of a camera interface they have display hardware and so on. Aside from the above points the big difference about these chips is that they include a second Cortex A7 core. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 15 +++++++++++++++ arch/arm/boot/dts/mstar-v7.dtsi | 2 +- arch/arm/mach-mstar/mstarv7.c | 1 + 3 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/mstar-infinity2m.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi new file mode 100644 index 000000000000..02adb9fe9d3c --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-infinity.dtsi" + +&cpus { + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; +}; diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 07fc46c7b4d4..2862b32c7f63 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -13,7 +13,7 @@ / { #size-cells = <1>; interrupt-parent = <&gic>; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c index 81a4cbcab206..1aa748fa006e 100644 --- a/arch/arm/mach-mstar/mstarv7.c +++ b/arch/arm/mach-mstar/mstarv7.c @@ -35,6 +35,7 @@ static void __iomem *l3bridge; static const char * const mstarv7_board_dt_compat[] __initconst = { "mstar,infinity", + "mstar,infinity2m", "mstar,infinity3", "mstar,mercury5", NULL,