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IronPort-SDR: pjd57PINjurwEY6w+ve5EXW3sJ56RR2Y3cUkOPllhn1HSfO+QFjkukcDT/rRqfLf0WJHPNRxz4 RvWYhJ1uUW4RSy1ogmEBUbYpElnSXGzKd/ria+fPqBY0NvSK7g+Nr1SByJeK2wQ03F9B8IBpdd k+RNEXC5QiZAWbD1mGdQcEFuXmT+ZFwPTC4uTSy18A16zn69PZbgU3UE56zsyeQyfqYiGBv6Yc 3Z+5Gu8wSnFow7r9ZSmTRu8/eU2FFZGczPtOM6KiGqXnHid0QWE8zwhvNBM7pu34M2QwE46bfy hBQ= X-IronPort-AV: E=Sophos;i="5.78,405,1599548400"; d="scan'208";a="101529653" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Dec 2020 07:28:22 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 9 Dec 2020 07:28:21 -0700 Received: from soft-dev10.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 9 Dec 2020 07:28:19 -0700 From: Lars Povlsen To: Linus Walleij , Rob Herring Subject: [PATCH -next 2/3] dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add irq support Date: Wed, 9 Dec 2020 15:27:52 +0100 Message-ID: <20201209142753.683208-3-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201209142753.683208-1-lars.povlsen@microchip.com> References: <20201209142753.683208-1-lars.povlsen@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201209_092823_148913_B699720D X-CRM114-Status: GOOD ( 11.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Alexandre Belloni , linux-kernel@vger.kernel.org, Microchip Linux Driver Support , linux-gpio@vger.kernel.org, Lars Povlsen , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This describe the new bindings for the added IRQ support in the pinctrl-microchip-sgpio driver. Signed-off-by: Lars Povlsen Reviewed-by: Rob Herring --- .../bindings/pinctrl/microchip,sparx5-sgpio.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml index 08325bf77a81..df0c83cb1c6e 100644 --- a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml @@ -91,6 +91,18 @@ patternProperties: controlled indirectly by the "ngpios" property: (ngpios/32). const: 3 + interrupts: + description: Specifies the sgpio IRQ (in parent controller) + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: + Specifies the pin (port and bit) and flags, as defined in + defined in include/dt-bindings/interrupt-controller/irq.h + const: 3 + ngpios: description: The numbers of GPIO's exposed. This must be a multiple of 32. @@ -118,6 +130,7 @@ required: examples: - | + #include sgpio2: gpio@1101059c { #address-cells = <1>; #size-cells = <0>; @@ -134,6 +147,9 @@ examples: gpio-controller; #gpio-cells = <3>; ngpios = <96>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; }; sgpio_out2: gpio@1 { compatible = "microchip,sparx5-sgpio-bank";