From patchwork Fri Dec 11 03:17:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Billy Tsai X-Patchwork-Id: 11967149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31BBFC4361B for ; Fri, 11 Dec 2020 03:20:31 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B63D523EAF for ; Fri, 11 Dec 2020 03:20:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B63D523EAF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=AkPRVmFj6Ay2seHNqBcUpZEqmoe/iCmD2L3/S50suSE=; b=aJDWPM9ypxZAY2ygY+naMtzfG7 qGMbKHA+akyNN5Xd+2SChgMF+KMH1ldPrZEVS1Jz78os0B2sYeHuoVa0lf4wWq0xZYYbAyavXOado j/CPOGETsScNhboUnMNknrSxf7uw9VibfUS6Mpf/lIe8POL9httJQpPgas7UGUQY3/GAoNlKE+b5L NW1zJNvEDaCDoxqbS5Jo1Kf+gDH3oNSWSbeCLLBDS/XE28I4VJXa6cF+8jtmuYSpa5BrdJveAqojL SS15BiNBaI7VNSXtBo2MDjDqe2juZRxgEjiYuz3EyN2jBVyGEo7ZDMKVIUTzLW17vA5BdapDxUVDJ c8AW5++Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1knYxa-0003G7-U8; Fri, 11 Dec 2020 03:19:10 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1knYxZ-0003Fs-HK for linux-arm-kernel@merlin.infradead.org; Fri, 11 Dec 2020 03:19:09 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Type:Content-Transfer-Encoding: MIME-Version:Message-ID:Date:Subject:CC:To:From:Sender:Reply-To:Content-ID: Content-Description:In-Reply-To:References; bh=GgNvbe+EPRpeZDdlbgKIdV04B1f1oDtYWccQEAonv98=; b=dg2lv/bkRcr/dvNTivCdkhnqMd F+9E6tPJ/Zz98NhHstFl+48RUHB6bBdRQyFpljV6ya5nabBvb5Dudl13M1WpQt1T+FpjY7uNzEUxq 0zLSDYOyHIRidtQUUBWEik8NSJ18THl98liW8/ZeYJkSLBqKENRLN9wMJaT8P5Sgtl99aVqrns8j8 guKJe/B+iulgoSsdhFQucXcjZDSP/xgr1Ir0up9YFPR8vQEEkX1iETtIXvelCnBIAJCM8N6WuOq5t huvDEoBCwuOLatTJscQIZ1VubdX3KDzPleJslYv851JYhtpOo+bZM0QhQjf8YFH3qjIbBiYhjo4rE 6bpoXRiA==; Received: from twspam01.aspeedtech.com ([211.20.114.71]) by casper.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1knYxU-0007pS-Pn for linux-arm-kernel@lists.infradead.org; Fri, 11 Dec 2020 03:19:08 +0000 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 0BB3EfHa057144; Fri, 11 Dec 2020 11:14:41 +0800 (GMT-8) (envelope-from billy_tsai@aspeedtech.com) Received: from BillyTsai-pc.aspeed.com (192.168.2.149) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Dec 2020 11:17:39 +0800 From: Billy Tsai To: , , , , , , , Subject: [PATCH] driver: aspeed: g6: Fix PWMG0 pinctrl setting Date: Fri, 11 Dec 2020 11:17:41 +0800 Message-ID: <20201211031741.23711-1-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [192.168.2.149] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 0BB3EfHa057144 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201211_031905_768527_1E2F69B3 X-CRM114-Status: UNSURE ( 7.06 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: BMC-SW@aspeedtech.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from SCU414 to SCU4B4. Besides that, When PWM8~15 of PWMG0 set it needs to clear SCU414 bits at the same time. Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Billy Tsai --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 26 ++++++++++++++-------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 34803a6c7664..6e61f045936f 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -346,50 +346,58 @@ FUNC_GROUP_DECL(RGMII4, F24, E23, E24, E25, D26, D24, C25, C26, C24, B26, B25, FUNC_GROUP_DECL(RMII4, F24, E23, E24, E25, C25, C24, B26, B25, B24); #define D22 40 -SIG_EXPR_LIST_DECL_SESG(D22, SD1CLK, SD1, SIG_DESC_SET(SCU414, 8)); -SIG_EXPR_LIST_DECL_SEMG(D22, PWM8, PWM8G0, PWM8, SIG_DESC_SET(SCU414, 8)); +SIG_EXPR_LIST_DECL_SESG(D22, SD1CLK, SD1, SIG_DESC_SET(SCU414, 8)) +SIG_EXPR_LIST_DECL_SEMG(D22, PWM8, PWM8G0, PWM8, SIG_DESC_SET(SCU4B4, 8), + SIG_DESC_CLEAR(SCU414, 8)); PIN_DECL_2(D22, GPIOF0, SD1CLK, PWM8); GROUP_DECL(PWM8G0, D22); #define E22 41 SIG_EXPR_LIST_DECL_SESG(E22, SD1CMD, SD1, SIG_DESC_SET(SCU414, 9)); -SIG_EXPR_LIST_DECL_SEMG(E22, PWM9, PWM9G0, PWM9, SIG_DESC_SET(SCU4B4, 9)); +SIG_EXPR_LIST_DECL_SEMG(E22, PWM9, PWM9G0, PWM9, SIG_DESC_SET(SCU4B4, 9), + SIG_DESC_CLEAR(SCU414, 9)); PIN_DECL_2(E22, GPIOF1, SD1CMD, PWM9); GROUP_DECL(PWM9G0, E22); #define D23 42 SIG_EXPR_LIST_DECL_SESG(D23, SD1DAT0, SD1, SIG_DESC_SET(SCU414, 10)); -SIG_EXPR_LIST_DECL_SEMG(D23, PWM10, PWM10G0, PWM10, SIG_DESC_SET(SCU4B4, 10)); +SIG_EXPR_LIST_DECL_SEMG(D23, PWM10, PWM10G0, PWM10, SIG_DESC_SET(SCU4B4, 10), + SIG_DESC_CLEAR(SCU414, 10)); PIN_DECL_2(D23, GPIOF2, SD1DAT0, PWM10); GROUP_DECL(PWM10G0, D23); #define C23 43 SIG_EXPR_LIST_DECL_SESG(C23, SD1DAT1, SD1, SIG_DESC_SET(SCU414, 11)); -SIG_EXPR_LIST_DECL_SEMG(C23, PWM11, PWM11G0, PWM11, SIG_DESC_SET(SCU4B4, 11)); +SIG_EXPR_LIST_DECL_SEMG(C23, PWM11, PWM11G0, PWM11, SIG_DESC_SET(SCU4B4, 11), + SIG_DESC_CLEAR(SCU414, 11)); PIN_DECL_2(C23, GPIOF3, SD1DAT1, PWM11); GROUP_DECL(PWM11G0, C23); #define C22 44 SIG_EXPR_LIST_DECL_SESG(C22, SD1DAT2, SD1, SIG_DESC_SET(SCU414, 12)); -SIG_EXPR_LIST_DECL_SEMG(C22, PWM12, PWM12G0, PWM12, SIG_DESC_SET(SCU4B4, 12)); +SIG_EXPR_LIST_DECL_SEMG(C22, PWM12, PWM12G0, PWM12, SIG_DESC_SET(SCU4B4, 12), + SIG_DESC_CLEAR(SCU414, 12)); PIN_DECL_2(C22, GPIOF4, SD1DAT2, PWM12); GROUP_DECL(PWM12G0, C22); #define A25 45 SIG_EXPR_LIST_DECL_SESG(A25, SD1DAT3, SD1, SIG_DESC_SET(SCU414, 13)); -SIG_EXPR_LIST_DECL_SEMG(A25, PWM13, PWM13G0, PWM13, SIG_DESC_SET(SCU4B4, 13)); +SIG_EXPR_LIST_DECL_SEMG(A25, PWM13, PWM13G0, PWM13, SIG_DESC_SET(SCU4B4, 13), + SIG_DESC_CLEAR(SCU414, 13)); PIN_DECL_2(A25, GPIOF5, SD1DAT3, PWM13); GROUP_DECL(PWM13G0, A25); #define A24 46 SIG_EXPR_LIST_DECL_SESG(A24, SD1CD, SD1, SIG_DESC_SET(SCU414, 14)); -SIG_EXPR_LIST_DECL_SEMG(A24, PWM14, PWM14G0, PWM14, SIG_DESC_SET(SCU4B4, 14)); +SIG_EXPR_LIST_DECL_SEMG(A24, PWM14, PWM14G0, PWM14, SIG_DESC_SET(SCU4B4, 14), + SIG_DESC_CLEAR(SCU414, 14)); PIN_DECL_2(A24, GPIOF6, SD1CD, PWM14); GROUP_DECL(PWM14G0, A24); #define A23 47 SIG_EXPR_LIST_DECL_SESG(A23, SD1WP, SD1, SIG_DESC_SET(SCU414, 15)); -SIG_EXPR_LIST_DECL_SEMG(A23, PWM15, PWM15G0, PWM15, SIG_DESC_SET(SCU4B4, 15)); +SIG_EXPR_LIST_DECL_SEMG(A23, PWM15, PWM15G0, PWM15, SIG_DESC_SET(SCU4B4, 15), + SIG_DESC_CLEAR(SCU414, 15)); PIN_DECL_2(A23, GPIOF7, SD1WP, PWM15); GROUP_DECL(PWM15G0, A23);