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Thu, 24 Dec 2020 05:17:37 -0600 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:17:37 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:17:37 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBGWGI116630; Thu, 24 Dec 2020 05:17:33 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Philipp Zabel Subject: [PATCH v3 12/15] arm64: dts: ti: k3-j721e-main: Add DT nodes for clocks within Sierra SERDES Date: Thu, 24 Dec 2020 16:46:24 +0530 Message-ID: <20201224111627.32590-13-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224111627.32590-1-kishon@ti.com> References: <20201224111627.32590-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_061739_956796_6E6674F4 X-CRM114-Status: GOOD ( 11.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add DT nodes for clocks within Sierra SERDES. Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 128 ++++++++++++++++++++-- 1 file changed, 120 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 2d526ea44a85..9d1edce31829 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -400,8 +400,36 @@ #size-cells = <0>; resets = <&serdes_wiz0 0>; reset-names = "sierra_reset"; - clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, <&serdes0_pll_cmnlc>, <&serdes0_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; + + serdes0_refrcv: refrcv { + clocks = <&wiz0_pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes0_refrcv1: refrcv1 { + clocks = <&wiz0_pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes0_pll_cmnlc: pll_cmnlc { + clocks = <&wiz0_pll0_refclk>, <&serdes0_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes0_pll_cmnlc>; + assigned-clock-parents = <&wiz0_pll0_refclk>; + }; + + serdes0_pll_cmnlc1: pll_cmnlc1 { + clocks = <&wiz0_pll1_refclk>, <&serdes0_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes0_pll_cmnlc1>; + assigned-clock-parents = <&wiz0_pll1_refclk>; + }; }; }; @@ -457,8 +485,36 @@ #size-cells = <0>; resets = <&serdes_wiz1 0>; reset-names = "sierra_reset"; - clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, <&serdes1_pll_cmnlc>, <&serdes1_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; + + serdes1_refrcv: refrcv { + clocks = <&wiz1_pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes1_refrcv1: refrcv1 { + clocks = <&wiz1_pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes1_pll_cmnlc: pll_cmnlc { + clocks = <&wiz1_pll0_refclk>, <&serdes1_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes1_pll_cmnlc>; + assigned-clock-parents = <&wiz1_pll0_refclk>; + }; + + serdes1_pll_cmnlc1: pll_cmnlc1 { + clocks = <&wiz1_pll1_refclk>, <&serdes1_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes1_pll_cmnlc1>; + assigned-clock-parents = <&wiz1_pll1_refclk>; + }; }; }; @@ -514,8 +570,36 @@ #size-cells = <0>; resets = <&serdes_wiz2 0>; reset-names = "sierra_reset"; - clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, <&serdes2_pll_cmnlc>, <&serdes2_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; + + serdes2_refrcv: refrcv { + clocks = <&wiz2_pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes2_refrcv1: refrcv1 { + clocks = <&wiz2_pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes2_pll_cmnlc: pll_cmnlc { + clocks = <&wiz2_pll0_refclk>, <&serdes2_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes2_pll_cmnlc>; + assigned-clock-parents = <&wiz2_pll0_refclk>; + }; + + serdes2_pll_cmnlc1: pll_cmnlc1 { + clocks = <&wiz2_pll1_refclk>, <&serdes2_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes2_pll_cmnlc1>; + assigned-clock-parents = <&wiz2_pll1_refclk>; + }; }; }; @@ -571,8 +655,36 @@ #size-cells = <0>; resets = <&serdes_wiz3 0>; reset-names = "sierra_reset"; - clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, <&serdes3_pll_cmnlc>, <&serdes3_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; + + serdes3_refrcv: refrcv { + clocks = <&wiz3_pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes3_refrcv1: refrcv1 { + clocks = <&wiz3_pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes3_pll_cmnlc: pll_cmnlc { + clocks = <&wiz3_pll0_refclk>, <&serdes3_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes3_pll_cmnlc>; + assigned-clock-parents = <&wiz3_pll0_refclk>; + }; + + serdes3_pll_cmnlc1: pll_cmnlc1 { + clocks = <&wiz3_pll1_refclk>, <&serdes3_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes3_pll_cmnlc1>; + assigned-clock-parents = <&wiz3_pll1_refclk>; + }; }; };