From patchwork Tue Dec 29 11:47:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 11992229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DAFEC433DB for ; Tue, 29 Dec 2020 11:50:13 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BB516206DC for ; Tue, 29 Dec 2020 11:50:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BB516206DC Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=THSu72AVj/y2Ew8z62/c6BeJQi6XlcdpcWaG7G2U4y8=; b=l/6sYBWSWuobJCUU2A0GAJHt+ pIeSdRg/BRAXSNnIL0dYW8Tmsx9Nhs86bfOSf+8NDCJOgTqZYNYsHbMTJ5l5b1z+Y3l0bBEUD9lWp aWA7CGjl7adySrqypAgNaDQIQ3ZfJWUamFZh6SqhIa17D8BislH4Kq69i7Rip2N5g5PgUO7u5Ywrl P7Evi+C3MPtGUbr1IfntnxfriQG1i38FH0fwMOt5u9ST1OvyIobYkv3Q5uR6x4ENKLjxVZb07wRXO otm0pAZy6ujmmSWncAug1mMW+ULCFQrZ2/ohFVQba7P379CU3bzVYOMBeBJ/GwhvOmuWtZR23vH4i AsBRJkD3g==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kuDUV-0003Ec-57; Tue, 29 Dec 2020 11:48:39 +0000 Received: from ssl.serverraum.org ([2a01:4f8:151:8464::1:2]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kuDTw-000334-PV for linux-arm-kernel@lists.infradead.org; Tue, 29 Dec 2020 11:48:11 +0000 Received: from mwalle01.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:fa59:71ff:fe9b:b851]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 2259523E63; Tue, 29 Dec 2020 12:47:54 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1609242474; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FOmKeCjYomUUA6VaUP8Rbhpromvfdll+dp4HcVM/W78=; b=qD3jFqKERK670FbKBkfLhLb8/1JJF7d9G7/18B6LfRPmmOxcmdKXITkjJwwsaCWS2Vzv60 HyXfh3IfM3ZIKI6i+43j8opEh6NSoKYKdCOUMmFFzmEC6v5K17tVmSj+BlQts1nyqaVT/g sg/eLLmkBXa2z7sTsxB5ILmUhobb71Q= From: Michael Walle To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] arm64: dts: lx2160a: use constants in the clockgen phandle Date: Tue, 29 Dec 2020 12:47:40 +0100 Message-Id: <20201229114740.7936-8-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201229114740.7936-1-michael@walle.cc> References: <20201229114740.7936-1-michael@walle.cc> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201229_064805_176901_A54AD13C X-CRM114-Status: GOOD ( 11.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Walle , Rob Herring , Shawn Guo , Li Yang Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that we have constants, use them. This is just a mechanical change. Signed-off-by: Michael Walle --- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 92 ++++++++++++------- 1 file changed, 57 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 197397777c83..b16e7f738f52 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -4,6 +4,7 @@ // // Copyright 2018-2020 NXP +#include #include #include #include @@ -30,7 +31,7 @@ compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x0>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -47,7 +48,7 @@ compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x1>; - clocks = <&clockgen 1 0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -64,7 +65,7 @@ compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x100>; - clocks = <&clockgen 1 1>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -81,7 +82,7 @@ compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x101>; - clocks = <&clockgen 1 1>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -98,7 +99,7 @@ compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x200>; - clocks = <&clockgen 1 2>; + clocks = <&clockgen QORIQ_CLK_CMUX 2>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -115,7 +116,7 @@ compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x201>; - clocks = <&clockgen 1 2>; + clocks = <&clockgen QORIQ_CLK_CMUX 2>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -132,7 +133,7 @@ compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x300>; - clocks = <&clockgen 1 3>; + clocks = <&clockgen QORIQ_CLK_CMUX 3>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -149,7 +150,7 @@ compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x301>; - clocks = <&clockgen 1 3>; + clocks = <&clockgen QORIQ_CLK_CMUX 3>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -166,7 +167,7 @@ compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x400>; - clocks = <&clockgen 1 4>; + clocks = <&clockgen QORIQ_CLK_CMUX 4>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -183,7 +184,7 @@ compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x401>; - clocks = <&clockgen 1 4>; + clocks = <&clockgen QORIQ_CLK_CMUX 4>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -200,7 +201,7 @@ compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x500>; - clocks = <&clockgen 1 5>; + clocks = <&clockgen QORIQ_CLK_CMUX 5>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -217,7 +218,7 @@ compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x501>; - clocks = <&clockgen 1 5>; + clocks = <&clockgen QORIQ_CLK_CMUX 5>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -234,7 +235,7 @@ compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x600>; - clocks = <&clockgen 1 6>; + clocks = <&clockgen QORIQ_CLK_CMUX 6>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -251,7 +252,7 @@ compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x601>; - clocks = <&clockgen 1 6>; + clocks = <&clockgen QORIQ_CLK_CMUX 6>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -268,7 +269,7 @@ compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x700>; - clocks = <&clockgen 1 7>; + clocks = <&clockgen QORIQ_CLK_CMUX 7>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -285,7 +286,7 @@ compatible = "arm,cortex-a72"; enable-method = "psci"; reg = <0x701>; - clocks = <&clockgen 1 7>; + clocks = <&clockgen QORIQ_CLK_CMUX 7>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; @@ -685,7 +686,8 @@ reg = <0x0 0x2000000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; status = "disabled"; }; @@ -697,7 +699,8 @@ reg = <0x0 0x2010000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; status = "disabled"; }; @@ -708,7 +711,8 @@ reg = <0x0 0x2020000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; status = "disabled"; }; @@ -719,7 +723,8 @@ reg = <0x0 0x2030000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; status = "disabled"; }; @@ -730,7 +735,8 @@ reg = <0x0 0x2040000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; status = "disabled"; }; @@ -742,7 +748,8 @@ reg = <0x0 0x2050000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; status = "disabled"; }; @@ -753,7 +760,8 @@ reg = <0x0 0x2060000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; status = "disabled"; }; @@ -764,7 +772,8 @@ reg = <0x0 0x2070000 0x0 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&clockgen 4 15>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; status = "disabled"; }; @@ -776,7 +785,10 @@ <0x0 0x20000000 0x0 0x10000000>; reg-names = "fspi_base", "fspi_mmap"; interrupts = ; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; clock-names = "fspi_en", "fspi"; status = "disabled"; }; @@ -787,7 +799,8 @@ #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 7>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; clock-names = "dspi"; spi-num-chipselects = <5>; bus-num = <0>; @@ -800,7 +813,8 @@ #size-cells = <0>; reg = <0x0 0x2110000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 7>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; clock-names = "dspi"; spi-num-chipselects = <5>; bus-num = <1>; @@ -813,7 +827,8 @@ #size-cells = <0>; reg = <0x0 0x2120000 0x0 0x10000>; interrupts = ; - clocks = <&clockgen 4 7>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; clock-names = "dspi"; spi-num-chipselects = <5>; bus-num = <2>; @@ -824,7 +839,8 @@ compatible = "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; interrupts = <0 28 0x4>; /* Level high type */ - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; dma-coherent; voltage-ranges = <1800 1800 3300 3300>; sdhci,auto-cmd12; @@ -837,7 +853,8 @@ compatible = "fsl,esdhc"; reg = <0x0 0x2150000 0x0 0x10000>; interrupts = <0 63 0x4>; /* Level high type */ - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; dma-coherent; voltage-ranges = <1800 1800 3300 3300>; sdhci,auto-cmd12; @@ -973,7 +990,8 @@ <0x7 0x100520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = ; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; dma-coherent; status = "disabled"; }; @@ -984,7 +1002,8 @@ <0x7 0x100520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = ; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; dma-coherent; status = "disabled"; }; @@ -995,7 +1014,8 @@ <0x7 0x100520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = ; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; dma-coherent; status = "disabled"; }; @@ -1006,7 +1026,8 @@ <0x7 0x100520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = ; - clocks = <&clockgen 4 3>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; dma-coherent; status = "disabled"; }; @@ -1279,7 +1300,8 @@ ptp-timer@8b95000 { compatible = "fsl,dpaa2-ptp"; reg = <0x0 0x8b95000 0x0 0x100>; - clocks = <&clockgen 4 1>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; little-endian; fsl,extts-fifo; };