From patchwork Wed Jan 6 19:28:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Giulio Benetti X-Patchwork-Id: 12002115 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F237AC433E9 for ; Wed, 6 Jan 2021 19:31:54 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A981C2311B for ; Wed, 6 Jan 2021 19:31:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A981C2311B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=micronovasrl.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ZDiCGJ2TkKX74QQmiaxrrkvpUqZtX7MvZEtRWl30zIw=; b=xbMRrF3ZclbwhpsgtX2pC3VDx ip0x3Idpk3gv12Rs0y+77fZhBMnMt45GDExicrNQmqJi9z5d20OJInVAS83yn+sDWbtx1Fo7eyt9F CyO2VpQP0OqC1fwL4rNqZ9vCINjq3KaOXfduVQNvlvOFchMEcccZkKqjtxgwIq9baaztufvJSzVj0 HcbHEHYiJRZgqjNANjlKQTsv1qUnj4nxE1GyfM1XES+Jmx+tlyVZx6qCy+N71WQVsm+HAAVUFeVon NG8+zOuURz2I9uBprwSAO5wZ7Ga+EeU9LKG3UzaREnzTXd8LCMJU/NPqI9VRL4hyKcIveAIQcgBih JmYZtRiaQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kxEVe-0008AQ-SN; Wed, 06 Jan 2021 19:30:18 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kxEVd-0008AB-UK for linux-arm-kernel@merlin.infradead.org; Wed, 06 Jan 2021 19:30:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-ID:Content-Description; bh=4KB7nQE2HfQNE9MLWN0xXYo5db7LaXQEjErlNoR7iiw=; b=SMj8eZ8dKepqgi+NPeIEpGsen/ gkFQJsLp40QMdD3QfxS+jVyfZp6yyatUsvvgjS6y9YmfUEmfdqBAUHlJ9TW2l0L2nrIs/R9N2m7z0 rkINjc4i/SzL/ouc/YJfaWgEa3fKgqzoz5qnVz+e0MPyV4MdwStIIDsRqtUbi1t7WKRQMqtcTHeTH 7qX1n+2SysHASbIjLENsBmNGyZw3nwtovem1mRcLG86opQSAmQoxwftY+/UARNyS8/J1jjXNr0L3p YaRPcc8ZzzsGda6fU3TeweVuVCu4KzNzg86i4Rzh1NpFuOY/Q+KYKOwOsb33lZd4qfpPm3WtgGloF dg0vOhJg==; Received: from mail.micronovasrl.com ([212.103.203.10]) by casper.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1kxEUA-002dcU-5b for linux-arm-kernel@lists.infradead.org; Wed, 06 Jan 2021 19:29:43 +0000 Received: from mail.micronovasrl.com (mail.micronovasrl.com [127.0.0.1]) by mail.micronovasrl.com (Postfix) with ESMTP id 87ECEB045F4 for ; Wed, 6 Jan 2021 20:28:05 +0100 (CET) Authentication-Results: mail.micronovasrl.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=micronovasrl.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=micronovasrl.com; h=content-transfer-encoding:content-type:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :date:subject:subject:to:from:from; s=dkim; t=1609961285; x= 1610825286; bh=ve6PpitMBRMOaeoWwDbFW/+W2p3l0jAVa8GJuKa7cPU=; b=b ApMn1yPa/M9MRkOLZrYDeqI1D0qJ0zs/K4MEj3eASbCXv0hzGbkCmnpvv8YwCnR8 JzC1hi8ZRaDlTORuM0lkNBNqCmhWUSZS9kyG7GZfXdl1uUWzvuovJGZ3srZqxp9i a2JYntIWh2BNlRNSOruxcDm1PQ3Rrk8EohRME9GkRs= X-Virus-Scanned: Debian amavisd-new at mail.micronovasrl.com Received: from mail.micronovasrl.com ([127.0.0.1]) by mail.micronovasrl.com (mail.micronovasrl.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id qBMAw9M3Mzmi for ; Wed, 6 Jan 2021 20:28:05 +0100 (CET) Received: from ubuntu.localdomain (146-241-198-163.dyn.eolo.it [146.241.198.163]) by mail.micronovasrl.com (Postfix) with ESMTPSA id D3D2DB04586; Wed, 6 Jan 2021 20:28:02 +0100 (CET) From: Giulio Benetti To: Maxime Ripard Subject: [PATCH 2/2] drm/sun4i: tcon: improve DCLK polarity handling Date: Wed, 6 Jan 2021 20:28:00 +0100 Message-Id: <20210106192800.164052-3-giulio.benetti@micronovasrl.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210106192800.164052-1-giulio.benetti@micronovasrl.com> References: <20210106192800.164052-1-giulio.benetti@micronovasrl.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210106_192943_222559_D6604140 X-CRM114-Status: GOOD ( 12.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jernej Skrabec , airlied@linux.ie, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, wens@csie.org, linux-arm-kernel@lists.infradead.org, daniel@ffwll.ch, treding@nvidia.com, Giulio Benetti , Marjan Pascolo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org It turned out(Maxime suggestion) that bit 26 of SUN4I_TCON0_IO_POL_REG is dedicated to invert DCLK polarity and this makes thing really easier than before. So let's handle DCLK polarity by adding SUN4I_TCON0_IO_POL_DCLK_POSITIVE as bit 26 and activating according to bus_flags the same way is done for all the other signals. Cc: Maxime Ripard Signed-off-by: Giulio Benetti --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 20 +------------------- drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 + 2 files changed, 2 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index 52598bb0fb0b..30171ccd87e5 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -569,26 +569,8 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE; - /* - * On A20 and similar SoCs, the only way to achieve Positive Edge - * (Rising Edge), is setting dclk clock phase to 2/3(240°). - * By default TCON works in Negative Edge(Falling Edge), - * this is why phase is set to 0 in that case. - * Unfortunately there's no way to logically invert dclk through - * IO_POL register. - * The only acceptable way to work, triple checked with scope, - * is using clock phase set to 0° for Negative Edge and set to 240° - * for Positive Edge. - * On A33 and similar SoCs there would be a 90° phase option, - * but it divides also dclk by 2. - * Following code is a way to avoid quirks all around TCON - * and DOTCLOCK drivers. - */ if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) - clk_set_phase(tcon->dclk, 0); - - if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) - clk_set_phase(tcon->dclk, 240); + val |= SUN4I_TCON0_IO_POL_DCLK_POSITIVE; regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h index cfbf4e6c1679..0ce71d10a31b 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h @@ -113,6 +113,7 @@ #define SUN4I_TCON0_IO_POL_REG 0x88 #define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28) #define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27) +#define SUN4I_TCON0_IO_POL_DCLK_POSITIVE BIT(26) #define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25) #define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24)