From patchwork Thu Jan 14 16:24:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steen Hegelund X-Patchwork-Id: 12020205 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7E0DC433E0 for ; Thu, 14 Jan 2021 16:25:56 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5A90822B2B for ; Thu, 14 Jan 2021 16:25:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5A90822B2B Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=rSabrVRySuAyN09T1LKCTQvTYQi68sECHtd+chCrQj4=; b=H+LIy+qienGrOB7d2U97pjEEN 1STMHdb5z4P1mKwlvWb5BTJYr2PvvCwRkkK+Wo1k4birj+LfPfNjBW0rSqrxJaI+SGAUM1hbn7LES 3bs2B4/Hq4iWl07eCi7VhjlQJjuciR7wKvGaHtjO2GdMEu4FMOgEnfRiVf+C/4yE+AKjb4GIWkqZR CZcX0Bwq+gHYVwnGzy7ofaQ9x7sNm8/BJ98bWzrzbiCh02cJ4GvbA+JDLfGzNn5gNkqRqbsq0exfo U6oToLZ5O5LjphBUlxjAxiv5XEAXFCq9EDcQviw3Kz7D0XMqY9BS9lYwxdIJ6EzV1M44aPXoZqws9 mF8Yeueig==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l05QU-0000od-9r; Thu, 14 Jan 2021 16:24:46 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l05QR-0000na-Jj for linux-arm-kernel@lists.infradead.org; Thu, 14 Jan 2021 16:24:44 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1610641484; x=1642177484; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5tDy1Ty/j0XhdbcBXXPw/CY2LnOTHbcQR+30q3Xoh7I=; b=u8RFfK5V1HgPcW0N9z86HGU2Fic2UNmzGbpbNfqqhJAALy/GLwc5SfvE EmVO1kaYOaWHxpM4eeXaEGjB2clr+s5YvdIlTfqalTERV2ghhMennhdiK NNF5HuAHUAYr/p2pJ8zWH1tQVZxw+eeZil78vUKYfJBYdxVJsv8HoZ03t jA2RxeVmVRsDmE2AWMEuZHa4ESCYtu/123ESIkq0BNdBL8j4otRvvpgso xdqasR0qbXK+xH2myhVWwgNYthpDPa3WaB+V9QKrq3BxOwHQPfW6bSs7H w4B0nb4ObtmE6guBIGr58k/TtPirTHFC+wNHCcvGH3Fn48IRa2t98x11M g==; IronPort-SDR: uQCiCBJ8CO5J0HpcLdEIFesXgHmvnyXupPU9XZUSYfb8ZzDavnSbvPGXp6T6u00TqlirDbu8hV 8wp44cxkiJUPdRLm4NYxDyavD4ELqcN4S2iOBVLNJysWUtpEXqezOYwEHelB/8t2/XLieoYE2x 1ISSeOcx/mAiYOClscUSZ52on/TToDFpJ5+qWS6BN8tfXXauvtBPUXZRMkHf5WfrD6Arbu9v3V cPI5x69QUHDc0+VJcZtWqFHFvfQ2Xuv8XtKNq2OxdFCbUb7f576oGoYd24J+8gINeGm5mxGl6Q WXA= X-IronPort-AV: E=Sophos;i="5.79,347,1602572400"; d="scan'208";a="105447446" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Jan 2021 09:24:43 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 14 Jan 2021 09:24:41 -0700 Received: from mchp-dev-shegelun.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 14 Jan 2021 09:24:39 -0700 From: Steen Hegelund To: Philipp Zabel , Rob Herring Subject: [PATCH v3 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings Date: Thu, 14 Jan 2021 17:24:30 +0100 Message-ID: <20210114162432.3039657-2-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210114162432.3039657-1-steen.hegelund@microchip.com> References: <20210114162432.3039657-1-steen.hegelund@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210114_112443_807079_3A556CAB X-CRM114-Status: GOOD ( 12.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Lunn , Alexandre Belloni , devicetree@vger.kernel.org, Steen Hegelund , linux-kernel@vger.kernel.org, Microchip Linux Driver Support , Gregory Clement , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Signed-off-by: Steen Hegelund --- .../bindings/reset/microchip,rst.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml b/Documentation/devicetree/bindings/reset/microchip,rst.yaml new file mode 100644 index 000000000000..af01016e246f --- /dev/null +++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip Sparx5 Switch Reset Controller + +maintainers: + - Steen Hegelund + - Lars Povlsen + +description: | + The Microchip Sparx5 Switch provides reset control and implements the following + functions + - One Time Switch Core Reset (Soft Reset) + +properties: + $nodename: + pattern: "^reset-controller@[0-9a-f]+$" + + compatible: + const: microchip,sparx5-switch-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + + cpu-syscon: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: syscon used to access CPU reset + maxItems: 1 + + gcb-syscon: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: syscon used to access Global Control Block + maxItems: 1 + +required: + - compatible + - reg + - "#reset-cells" + - cpu-syscon + - gcb-syscon + +additionalProperties: false + +examples: + - | + reset: reset-controller@0 { + compatible = "microchip,sparx5-switch-reset"; + reg = <0x0 0x0>; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; + gcb-syscon = <&gcb_ctrl>; + }; +