| Message ID | 20210118183033.41764-2-vincenzo.frascino@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: ARMv8.5-A: MTE: Add async mode support | expand |
On Mon, Jan 18, 2021 at 06:30:29PM +0000, Vincenzo Frascino wrote: > MTE provides an asynchronous mode for detecting tag exceptions. In > particular instead of triggering a fault the arm64 core updates a > register which is checked by the kernel after the asynchronous tag > check fault has occurred. > > Add support for MTE asynchronous mode. > > The exception handling mechanism will be added with a future patch. > > Note: KASAN HW activates async mode via kasan.mode kernel parameter. > The default mode is set to synchronous. > The code that verifies the status of TFSR_EL1 will be added with a > future patch. > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
On Mon, Jan 18, 2021 at 7:30 PM Vincenzo Frascino <vincenzo.frascino@arm.com> wrote: > > MTE provides an asynchronous mode for detecting tag exceptions. In > particular instead of triggering a fault the arm64 core updates a > register which is checked by the kernel after the asynchronous tag > check fault has occurred. > > Add support for MTE asynchronous mode. > > The exception handling mechanism will be added with a future patch. > > Note: KASAN HW activates async mode via kasan.mode kernel parameter. > The default mode is set to synchronous. > The code that verifies the status of TFSR_EL1 will be added with a > future patch. > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> > --- > arch/arm64/include/asm/memory.h | 3 ++- > arch/arm64/include/asm/mte-kasan.h | 9 +++++++-- > arch/arm64/kernel/mte.c | 16 ++++++++++++++-- > 3 files changed, 23 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h > index 18fce223b67b..233d9feec45c 100644 > --- a/arch/arm64/include/asm/memory.h > +++ b/arch/arm64/include/asm/memory.h > @@ -231,7 +231,8 @@ static inline const void *__tag_set(const void *addr, u8 tag) > } > > #ifdef CONFIG_KASAN_HW_TAGS > -#define arch_enable_tagging() mte_enable_kernel() > +#define arch_enable_tagging_sync() mte_enable_kernel_sync() > +#define arch_enable_tagging_async() mte_enable_kernel_async() > #define arch_init_tags(max_tag) mte_init_tags(max_tag) > #define arch_get_random_tag() mte_get_random_tag() > #define arch_get_mem_tag(addr) mte_get_mem_tag(addr) > diff --git a/arch/arm64/include/asm/mte-kasan.h b/arch/arm64/include/asm/mte-kasan.h > index 26349a4b5e2e..9a5e30dbe12a 100644 > --- a/arch/arm64/include/asm/mte-kasan.h > +++ b/arch/arm64/include/asm/mte-kasan.h > @@ -29,7 +29,8 @@ u8 mte_get_mem_tag(void *addr); > u8 mte_get_random_tag(void); > void *mte_set_mem_tag_range(void *addr, size_t size, u8 tag); > > -void mte_enable_kernel(void); > +void mte_enable_kernel_sync(void); > +void mte_enable_kernel_async(void); > void mte_init_tags(u64 max_tag); > > #else /* CONFIG_ARM64_MTE */ > @@ -52,7 +53,11 @@ static inline void *mte_set_mem_tag_range(void *addr, size_t size, u8 tag) > return addr; > } > > -static inline void mte_enable_kernel(void) > +static inline void mte_enable_kernel_sync(void) > +{ > +} > + > +static inline void mte_enable_kernel_sync(void) > { > } > > diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c > index dc9ada64feed..78fc079a3b1e 100644 > --- a/arch/arm64/kernel/mte.c > +++ b/arch/arm64/kernel/mte.c > @@ -151,11 +151,23 @@ void mte_init_tags(u64 max_tag) > write_sysreg_s(SYS_GCR_EL1_RRND | gcr_kernel_excl, SYS_GCR_EL1); > } > > -void mte_enable_kernel(void) > +static inline void __mte_enable_kernel(const char *mode, unsigned long tcf) > { > /* Enable MTE Sync Mode for EL1. */ > - sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, SCTLR_ELx_TCF_SYNC); > + sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, tcf); > isb(); > + > + pr_info_once("MTE: enabled in %s mode at EL1\n", mode); > +} > + > +void mte_enable_kernel_sync(void) > +{ > + __mte_enable_kernel("synchronous", SCTLR_ELx_TCF_SYNC); > +} > + > +void mte_enable_kernel_async(void) > +{ > + __mte_enable_kernel("asynchronous", SCTLR_ELx_TCF_ASYNC); > } > > static void update_sctlr_el1_tcf0(u64 tcf0) > -- > 2.30.0 > Reviewed-by: Andrey Konovalov <andreyknvl@google.com>
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h index 18fce223b67b..233d9feec45c 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -231,7 +231,8 @@ static inline const void *__tag_set(const void *addr, u8 tag) } #ifdef CONFIG_KASAN_HW_TAGS -#define arch_enable_tagging() mte_enable_kernel() +#define arch_enable_tagging_sync() mte_enable_kernel_sync() +#define arch_enable_tagging_async() mte_enable_kernel_async() #define arch_init_tags(max_tag) mte_init_tags(max_tag) #define arch_get_random_tag() mte_get_random_tag() #define arch_get_mem_tag(addr) mte_get_mem_tag(addr) diff --git a/arch/arm64/include/asm/mte-kasan.h b/arch/arm64/include/asm/mte-kasan.h index 26349a4b5e2e..9a5e30dbe12a 100644 --- a/arch/arm64/include/asm/mte-kasan.h +++ b/arch/arm64/include/asm/mte-kasan.h @@ -29,7 +29,8 @@ u8 mte_get_mem_tag(void *addr); u8 mte_get_random_tag(void); void *mte_set_mem_tag_range(void *addr, size_t size, u8 tag); -void mte_enable_kernel(void); +void mte_enable_kernel_sync(void); +void mte_enable_kernel_async(void); void mte_init_tags(u64 max_tag); #else /* CONFIG_ARM64_MTE */ @@ -52,7 +53,11 @@ static inline void *mte_set_mem_tag_range(void *addr, size_t size, u8 tag) return addr; } -static inline void mte_enable_kernel(void) +static inline void mte_enable_kernel_sync(void) +{ +} + +static inline void mte_enable_kernel_sync(void) { } diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c index dc9ada64feed..78fc079a3b1e 100644 --- a/arch/arm64/kernel/mte.c +++ b/arch/arm64/kernel/mte.c @@ -151,11 +151,23 @@ void mte_init_tags(u64 max_tag) write_sysreg_s(SYS_GCR_EL1_RRND | gcr_kernel_excl, SYS_GCR_EL1); } -void mte_enable_kernel(void) +static inline void __mte_enable_kernel(const char *mode, unsigned long tcf) { /* Enable MTE Sync Mode for EL1. */ - sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, SCTLR_ELx_TCF_SYNC); + sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, tcf); isb(); + + pr_info_once("MTE: enabled in %s mode at EL1\n", mode); +} + +void mte_enable_kernel_sync(void) +{ + __mte_enable_kernel("synchronous", SCTLR_ELx_TCF_SYNC); +} + +void mte_enable_kernel_async(void) +{ + __mte_enable_kernel("asynchronous", SCTLR_ELx_TCF_ASYNC); } static void update_sctlr_el1_tcf0(u64 tcf0)
MTE provides an asynchronous mode for detecting tag exceptions. In particular instead of triggering a fault the arm64 core updates a register which is checked by the kernel after the asynchronous tag check fault has occurred. Add support for MTE asynchronous mode. The exception handling mechanism will be added with a future patch. Note: KASAN HW activates async mode via kasan.mode kernel parameter. The default mode is set to synchronous. The code that verifies the status of TFSR_EL1 will be added with a future patch. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> --- arch/arm64/include/asm/memory.h | 3 ++- arch/arm64/include/asm/mte-kasan.h | 9 +++++++-- arch/arm64/kernel/mte.c | 16 ++++++++++++++-- 3 files changed, 23 insertions(+), 5 deletions(-)