From patchwork Wed Jan 20 13:43:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 12032417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D102C433DB for ; Wed, 20 Jan 2021 13:49:26 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8986C23357 for ; Wed, 20 Jan 2021 13:49:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8986C23357 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=uziTLuPqc2AiGJQ0KUyyJ5gfP6LIK9w7PbGefBafzNc=; b=0NWsUdu4AjRe2EeDmxUkj6fhs 0ihJY3RkYOPM3y+9RLETh/Q/WZxY9m/xCrIYy0CYqdVaEYavr0rUrs3xgQks5In16Jw/yXRqLWpEV ZBwewZd6gnm3yDkPhRndfH1YXgvBiklq23WuP4REx+5AxX7FmVeuXXV5lsWx8x0lE/dSEGdv3jSXq xzhDDH50OWwRMP2hr80UHSO6xV6gbxsFl1mcd6vxy20KhIPJCNBArRM+row3xVmBpibye7UBfF9sO X7e3nQnZwAZEk4c2ehCgYcHllE5NH1IY3jM2SFWu66y9C0k3NbLnGG7+aBQhjUPF6hJyDmwt/9yQi V1JOd0rxA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l2DpM-0002mE-Kt; Wed, 20 Jan 2021 13:47:16 +0000 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l2Dn4-0001mu-JC for linux-arm-kernel@lists.infradead.org; Wed, 20 Jan 2021 13:45:21 +0000 Received: by mail-wr1-x42e.google.com with SMTP id b5so403278wrr.10 for ; Wed, 20 Jan 2021 05:44:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H8THZGlSlSDtEvgRsLNltBDQqY7eROszvbFqzIm7p3c=; b=GGlCskYn158Zt8+g6Vvygukv5Jq+n5qwIXVmEltfRVT160z/dGlPo9qAJPg8URpcze mB0zjBFGbka7lWIY883nQ4jihFI8Sfbfg2ElmGMZdBePAs2dvHk6FnniO5CD23DrjPwm YRE05FogwagsOJSXs+TsEThMgE0aw0J5aUM5mJFc72c1zKCCcHiAKRoMtPv034wNIZtq F4Qpn4FD+jlEyW3RoCjbN00DlQmzSk+QvpQPFRiEoU5xvYv9U5DQVq43RVgFMoSz9duq 8Q9lapsO0ErYZS2vrStkUDIw99Af/TLay1bNehNWZOlM4aMf3yaulHB8nF8EyvZ67qOl tr/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H8THZGlSlSDtEvgRsLNltBDQqY7eROszvbFqzIm7p3c=; b=X6XfHC20F9kWnlRoMWDYdY6NwsHCjGaxXmnbN1yL+Gc9szGJjjHO3xwmjavgHdWi4Q 0YGbRpC7dLK2Xt9cHfO2fzwFeUZ/dYIhrBshPBaGH8Ufwou8Le2Cbdhgkfxdad4TdSW/ vHeqP3kq9T2fS7TcT+3cs70SSsEJgFOzLSs1kxTHZLjnEhjovklANtEXawbg6CxAa9Wr ReFpPimICB7waaDuj5sEoqG8AMdI0HQL7g7qBEYCFBMFshFEmZLgcZlgkvbmv3WSTPFy qx3f7UxyKu3SlDiwPB6HNcfa5xT/56iS9xg7f9sWKok03EK+LiDrsjlAg06PudpnBGkq N4rQ== X-Gm-Message-State: AOAM533S0iSGFX/xuuIZfdsBmaIs37yQAfAqiRdSsflcrLWmWUFzbW/U pHLtaO1yN3Wl/QLRbMbnJzqNQg== X-Google-Smtp-Source: ABdhPJw8BUxkA8o7OM0fmdCbO8qCsbtlXvSF3jtfnnxsoGNjwxoiJtQpQLdgRsYSXFp9Qj6jO+vwAw== X-Received: by 2002:a5d:58d7:: with SMTP id o23mr9598863wrf.288.1611150293130; Wed, 20 Jan 2021 05:44:53 -0800 (PST) Received: from localhost.localdomain ([2a02:2450:102f:d6a:93b3:1f80:ae7b:a5c6]) by smtp.gmail.com with ESMTPSA id t67sm4224075wmt.28.2021.01.20.05.44.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Jan 2021 05:44:52 -0800 (PST) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robert.foss@linaro.org, todor.too@gmail.com, mchehab@kernel.org, robh+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, leoyang.li@nxp.com, geert+renesas@glider.be, vkoul@kernel.org, Anson.Huang@nxp.com, michael@walle.cc, agx@sigxcpu.org, max.oss.09@gmail.com, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, AngeloGioacchino Del Regno , Andrey Konovalov , Laurent Pinchart Subject: [PATCH v2 14/22] dt-bindings: media: camss: Add qcom, msm8996-camss binding Date: Wed, 20 Jan 2021 14:43:49 +0100 Message-Id: <20210120134357.1522254-14-robert.foss@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210120134357.1522254-1-robert.foss@linaro.org> References: <20210120134357.1522254-1-robert.foss@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210120_084454_703806_E76C2DDE X-CRM114-Status: GOOD ( 16.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Azam Sadiq Pasha Kapatrala Syed , Sarvesh Sridutt , Jonathan Marek , Tomasz Figa Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add bindings for qcom,msm8996-camss in order to support the camera subsystem on MSM8996. Signed-off-by: Robert Foss --- Changes since v1: - Laurent: Reworked driver to use dtschema .../bindings/media/qcom,msm8996-camss.yaml | 418 ++++++++++++++++++ 1 file changed, 418 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,msm8996-camss.yaml diff --git a/Documentation/devicetree/bindings/media/qcom,msm8996-camss.yaml b/Documentation/devicetree/bindings/media/qcom,msm8996-camss.yaml new file mode 100644 index 000000000000..5ca0be8892ab --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,msm8996-camss.yaml @@ -0,0 +1,418 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/qcom,msm8996-camss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm CAMSS ISP + +maintainers: + - Robert Foss + - Todor Tomov + +description: | + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms + +properties: + compatible: + const: qcom,msm8996-camss + + clocks: + description: + Input clocks for the hardware block. + minItems: 36 + maxItems: 36 + + clock-names: + description: + Names of input clocks for the hardware block. + items: + - const: top_ahb + - const: ispif_ahb + - const: csiphy0_timer + - const: csiphy1_timer + - const: csiphy2_timer + - const: csi0_ahb + - const: csi0 + - const: csi0_phy + - const: csi0_pix + - const: csi0_rdi + - const: csi1_ahb + - const: csi1 + - const: csi1_phy + - const: csi1_pix + - const: csi1_rdi + - const: csi2_ahb + - const: csi2 + - const: csi2_phy + - const: csi2_pix + - const: csi2_rdi + - const: csi3_ahb + - const: csi3 + - const: csi3_phy + - const: csi3_pix + - const: csi3_rdi + - const: ahb + - const: vfe0 + - const: csi_vfe0 + - const: vfe0_ahb + - const: vfe0_stream + - const: vfe1 + - const: csi_vfe1 + - const: vfe1_ahb + - const: vfe1_stream + - const: vfe_ahb + - const: vfe_axi + + interrupts: + description: + IRQs for the hardware block. + minItems: 10 + maxItems: 10 + + interrupt-names: + description: + Names of IRQs for the hardware block. + items: + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid3 + - const: ispif + - const: vfe0 + - const: vfe1 + + iommus: + maxItems: 4 + + power-domains: + maxItems: 2 + + ports: + description: + The CSI data input ports. + + type: object + + properties: + port@0: + type: object + description: Input node for receiving CSI data. + properties: + endpoint: + type: object + + properties: + clock-lanes: + description: |- + The physical clock lane index. The value must + always be <7> as the hardware supports D-PHY + and C-PHY, indexes are in a common set and + D-PHY physical clock lane is labeled as 7. + + data-lanes: + description: |- + An array of physical data lanes indexes. + Position of an entry determines the logical + lane number, while the value of an entry + indicates physical lane index. Lane swapping + is supported. Physical lane indexes are: + 0, 1, 2, 3 + + required: + - clock-lanes + - data-lanes + + required: + - endpoint + - reg + + port@1: + type: object + description: Input node for receiving CSI data. + properties: + endpoint: + type: object + + properties: + clock-lanes: + description: |- + The physical clock lane index. The value must + always be <7> as the hardware supports D-PHY + and C-PHY, indexes are in a common set and + D-PHY physical clock lane is labeled as 7. + + data-lanes: + description: |- + An array of physical data lanes indexes. + Position of an entry determines the logical + lane number, while the value of an entry + indicates physical lane index. Lane swapping + is supported. Physical lane indexes are: + 0, 1, 2, 3 + + required: + - clock-lanes + - data-lanes + + required: + - endpoint + - reg + + port@2: + type: object + description: Input node for receiving CSI data. + properties: + endpoint: + type: object + + properties: + clock-lanes: + description: |- + The physical clock lane index. The value must + always be <7> as the hardware supports D-PHY + and C-PHY, indexes are in a common set and + D-PHY physical clock lane is labeled as 7. + + data-lanes: + description: |- + An array of physical data lanes indexes. + Position of an entry determines the logical + lane number, while the value of an entry + indicates physical lane index. Lane swapping + is supported. Physical lane indexes are: + 0, 1, 2, 3 + + required: + - clock-lanes + - data-lanes + + required: + - endpoint + - reg + + port@3: + type: object + description: Input node for receiving CSI data. + properties: + endpoint: + type: object + + properties: + clock-lanes: + description: |- + The physical clock lane index. The value must + always be <7> as the hardware supports D-PHY + and C-PHY, indexes are in a common set and + D-PHY physical clock lane is labeled as 7. + + data-lanes: + description: |- + An array of physical data lanes indexes. + Position of an entry determines the logical + lane number, while the value of an entry + indicates physical lane index. Lane swapping + is supported. Physical lane indexes are: + 0, 1, 2, 3 + + required: + - clock-lanes + - data-lanes + + required: + - endpoint + - reg + + reg: + minItems: 14 + maxItems: 14 + + reg-names: + items: + - const: csiphy0 + - const: csiphy0_clk_mux + - const: csiphy1 + - const: csiphy1_clk_mux + - const: csiphy2 + - const: csiphy2_clk_mux + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid3 + - const: ispif + - const: csi_clk_mux + - const: vfe0 + - const: vfe1 + + vdda-supply: + description: + Definition of the regulator used as analog power supply. + +required: + - clock-names + - clocks + - compatible + - interrupt-names + - interrupts + - iommus + - power-domains + - reg + - reg-names + - vdda-supply + +additionalProperties: false + +examples: + - | + #include + #include + #include + + camss: camss@a00000 { + compatible = "qcom,msm8996-camss"; + + clocks = <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_ISPIF_AHB_CLK>, + <&mmcc CAMSS_CSI0PHYTIMER_CLK>, + <&mmcc CAMSS_CSI1PHYTIMER_CLK>, + <&mmcc CAMSS_CSI2PHYTIMER_CLK>, + <&mmcc CAMSS_CSI0_AHB_CLK>, + <&mmcc CAMSS_CSI0_CLK>, + <&mmcc CAMSS_CSI0PHY_CLK>, + <&mmcc CAMSS_CSI0PIX_CLK>, + <&mmcc CAMSS_CSI0RDI_CLK>, + <&mmcc CAMSS_CSI1_AHB_CLK>, + <&mmcc CAMSS_CSI1_CLK>, + <&mmcc CAMSS_CSI1PHY_CLK>, + <&mmcc CAMSS_CSI1PIX_CLK>, + <&mmcc CAMSS_CSI1RDI_CLK>, + <&mmcc CAMSS_CSI2_AHB_CLK>, + <&mmcc CAMSS_CSI2_CLK>, + <&mmcc CAMSS_CSI2PHY_CLK>, + <&mmcc CAMSS_CSI2PIX_CLK>, + <&mmcc CAMSS_CSI2RDI_CLK>, + <&mmcc CAMSS_CSI3_AHB_CLK>, + <&mmcc CAMSS_CSI3_CLK>, + <&mmcc CAMSS_CSI3PHY_CLK>, + <&mmcc CAMSS_CSI3PIX_CLK>, + <&mmcc CAMSS_CSI3RDI_CLK>, + <&mmcc CAMSS_AHB_CLK>, + <&mmcc CAMSS_VFE0_CLK>, + <&mmcc CAMSS_CSI_VFE0_CLK>, + <&mmcc CAMSS_VFE0_AHB_CLK>, + <&mmcc CAMSS_VFE0_STREAM_CLK>, + <&mmcc CAMSS_VFE1_CLK>, + <&mmcc CAMSS_CSI_VFE1_CLK>, + <&mmcc CAMSS_VFE1_AHB_CLK>, + <&mmcc CAMSS_VFE1_STREAM_CLK>, + <&mmcc CAMSS_VFE_AHB_CLK>, + <&mmcc CAMSS_VFE_AXI_CLK>; + + clock-names = "top_ahb", + "ispif_ahb", + "csiphy0_timer", + "csiphy1_timer", + "csiphy2_timer", + "csi0_ahb", + "csi0", + "csi0_phy", + "csi0_pix", + "csi0_rdi", + "csi1_ahb", + "csi1", + "csi1_phy", + "csi1_pix", + "csi1_rdi", + "csi2_ahb", + "csi2", + "csi2_phy", + "csi2_pix", + "csi2_rdi", + "csi3_ahb", + "csi3", + "csi3_phy", + "csi3_pix", + "csi3_rdi", + "ahb", + "vfe0", + "csi_vfe0", + "vfe0_ahb", + "vfe0_stream", + "vfe1", + "csi_vfe1", + "vfe1_ahb", + "vfe1_stream", + "vfe_ahb", + "vfe_axi"; + + interrupts = , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "csiphy0", + "csiphy1", + "csiphy2", + "csid0", + "csid1", + "csid2", + "csid3", + "ispif", + "vfe0", + "vfe1"; + + iommus = <&vfe_smmu 0>, + <&vfe_smmu 1>, + <&vfe_smmu 2>, + <&vfe_smmu 3>; + + power-domains = <&mmcc VFE0_GDSC>, + <&mmcc VFE1_GDSC>; + + reg = <0x00a34000 0x1000>, + <0x00a00030 0x4>, + <0x00a35000 0x1000>, + <0x00a00038 0x4>, + <0x00a36000 0x1000>, + <0x00a00040 0x4>, + <0x00a30000 0x100>, + <0x00a30400 0x100>, + <0x00a30800 0x100>, + <0x00a30c00 0x100>, + <0x00a31000 0x500>, + <0x00a00020 0x10>, + <0x00a10000 0x1000>, + <0x00a14000 0x1000>; + + reg-names = "csiphy0", + "csiphy0_clk_mux", + "csiphy1", + "csiphy1_clk_mux", + "csiphy2", + "csiphy2_clk_mux", + "csid0", + "csid1", + "csid2", + "csid3", + "ispif", + "csi_clk_mux", + "vfe0", + "vfe1"; + + vdda-supply = <®_2v8>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; \ No newline at end of file