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Wed, 20 Jan 2021 09:17:58 -0800 (PST) X-Google-Smtp-Source: ABdhPJzbSbbQQqfi4fF3PmiXRlkX+5DNHzbFTBr8fiWRkMONP12dbuRjNvOpJ12jP2HbtPwj2PvqxA== X-Received: by 2002:adf:ffc8:: with SMTP id x8mr10346046wrs.158.1611163077975; Wed, 20 Jan 2021 09:17:57 -0800 (PST) Received: from redfedo.redhat.com ([2a01:cb14:499:3d00:cd47:f651:9d80:157a]) by smtp.gmail.com with ESMTPSA id o124sm5444077wmb.5.2021.01.20.09.17.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Jan 2021 09:17:57 -0800 (PST) From: Julien Thierry To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 5/5] arm64: Add load/store decoding helpers Date: Wed, 20 Jan 2021 18:17:45 +0100 Message-Id: <20210120171745.1657762-6-jthierry@redhat.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20210120171745.1657762-1-jthierry@redhat.com> References: <20210120171745.1657762-1-jthierry@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=jthierry@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210120_121801_638579_6DC353CD X-CRM114-Status: GOOD ( 11.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, catalin.marinas@arm.com, broonie@kernel.org, will@kernel.org, Julien Thierry Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Provide some function to group different load/store instructions. Signed-off-by: Julien Thierry --- arch/arm64/include/asm/aarch64-insn.h | 28 +++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/include/asm/aarch64-insn.h b/arch/arm64/include/asm/aarch64-insn.h index 3a0e0ad51f5b..f1b5b652c400 100644 --- a/arch/arm64/include/asm/aarch64-insn.h +++ b/arch/arm64/include/asm/aarch64-insn.h @@ -408,6 +408,34 @@ static inline bool aarch64_insn_is_barrier(u32 insn) aarch64_insn_is_isb(insn); } +static inline bool aarch64_insn_is_store_single(u32 insn) +{ + return aarch64_insn_is_store_imm(insn) || + aarch64_insn_is_store_pre(insn) || + aarch64_insn_is_store_post(insn); +} + +static inline bool aarch64_insn_is_store_pair(u32 insn) +{ + return aarch64_insn_is_stp(insn) || + aarch64_insn_is_stp_pre(insn) || + aarch64_insn_is_stp_post(insn); +} + +static inline bool aarch64_insn_is_load_single(u32 insn) +{ + return aarch64_insn_is_load_imm(insn) || + aarch64_insn_is_load_pre(insn) || + aarch64_insn_is_load_post(insn); +} + +static inline bool aarch64_insn_is_load_pair(u32 insn) +{ + return aarch64_insn_is_ldp(insn) || + aarch64_insn_is_ldp_pre(insn) || + aarch64_insn_is_ldp_post(insn); +} + enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn); bool aarch64_insn_uses_literal(u32 insn); bool aarch64_insn_is_branch(u32 insn);