| Message ID | 20210121182252.29320-1-lorenzo.pieralisi@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | irqchip/gic-v3: Fix typos in PMR/RPR SCR_EL3.FIQ handling explanation | expand |
On Thu, 21 Jan 2021 18:22:52 +0000, Lorenzo Pieralisi wrote: > The GICv3 driver explanation related to PMR/RPR and SCR_EL3.FIQ > secure/non-secure priority handling contains a couple of typos. > > Fix them. Applied to irq/irqchip-5.12, thanks! [1/1] irqchip/gic-v3: Fix typos in PMR/RPR SCR_EL3.FIQ handling explanation commit: d40341145a2497cb7a18d72fda53cd2220fe10f3 Cheers, M.
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 3fc65375cbe0..eb0ee356a629 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -75,10 +75,10 @@ static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); * are presented to the GIC CPUIF as follow: * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80; * - * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure + * If SCR_EL3.FIQ == 1, the values written to/read from PMR and RPR at non-secure * EL1 are subject to a similar operation thus matching the priorities presented * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0, - * these values are unchanched by the GIC. + * these values are unchanged by the GIC. * * see GICv3/GICv4 Architecture Specification (IHI0069D): * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
The GICv3 driver explanation related to PMR/RPR and SCR_EL3.FIQ secure/non-secure priority handling contains a couple of typos. Fix them. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Marc Zyngier <maz@kernel.org> --- drivers/irqchip/irq-gic-v3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)