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Signed-off-by: Joakim Zhang --- .../arch/arm64/freescale/imx8mq/sys/ddrc.json | 37 +++++++++++++++++++ .../arm64/freescale/imx8mq/sys/metrics.json | 18 +++++++++ 2 files changed, 55 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx8mq/sys/ddrc.json create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx8mq/sys/metrics.json diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx8mq/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/freescale/imx8mq/sys/ddrc.json new file mode 100644 index 000000000000..c8682728ddad --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx8mq/sys/ddrc.json @@ -0,0 +1,37 @@ +[ + { + "BriefDescription": "ddr cycles event", + "EventCode": "0x00", + "EventName": "imx8mq_ddr.cycles", + "Unit": "imx8_ddr", + "Compat": "i.MX8MQ" + }, + { + "BriefDescription": "ddr read-cycles event", + "EventCode": "0x2a", + "EventName": "imx8mq_ddr.read_cycles", + "Unit": "imx8_ddr", + "Compat": "i.MX8MQ" + }, + { + "BriefDescription": "ddr write-cycles event", + "EventCode": "0x2b", + "EventName": "imx8mq_ddr.write_cycles", + "Unit": "imx8_ddr", + "Compat": "i.MX8MQ" + }, + { + "BriefDescription": "ddr read event", + "EventCode": "0x35", + "EventName": "imx8mq_ddr.read", + "Unit": "imx8_ddr", + "Compat": "i.MX8MQ" + }, + { + "BriefDescription": "ddr write event", + "EventCode": "0x38", + "EventName": "imx8mq_ddr.write", + "Unit": "imx8_ddr", + "Compat": "i.MX8MQ" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx8mq/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/freescale/imx8mq/sys/metrics.json new file mode 100644 index 000000000000..862c98171e0d --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx8mq/sys/metrics.json @@ -0,0 +1,18 @@ +[ + { + "BriefDescription": "bytes all masters read from ddr based on read-cycles event", + "MetricName": "imx8mq_ddr_read.all", + "MetricExpr": "imx8mq_ddr.read_cycles * 4 * 4", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx8_ddr", + "Compat": "i.MX8MQ" + }, + { + "BriefDescription": "bytes all masters write to ddr based on write-cycles event", + "MetricName": "imx8mq_ddr_write.all", + "MetricExpr": "imx8mq_ddr.write_cycles * 4 * 4", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx8_ddr", + "Compat": "i.MX8MQ" + } +]