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Mon, 25 Jan 2021 17:57:15 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 25 Jan 2021 17:57:15 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 25 Jan 2021 17:57:14 -0600 Received: from lelv0597.itg.ti.com (lelv0597.itg.ti.com [10.181.64.32]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 10PNvEsH035804; Mon, 25 Jan 2021 17:57:14 -0600 Received: from localhost ([10.250.35.71]) by lelv0597.itg.ti.com (8.14.7/8.14.7) with ESMTP id 10PNvE3t117198; Mon, 25 Jan 2021 17:57:14 -0600 From: Suman Anna To: Bjorn Andersson , Rob Herring Subject: [PATCH 2/2] hwspinlock: omap: Add support for K3 AM64x SoCs Date: Mon, 25 Jan 2021 17:56:53 -0600 Message-ID: <20210125235653.24385-3-s-anna@ti.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210125235653.24385-1-s-anna@ti.com> References: <20210125235653.24385-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210125_185719_144335_3273D16B X-CRM114-Status: GOOD ( 14.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-omap@vger.kernel.org, linux-remoteproc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The AM64x SoC contains a HwSpinlock IP instance in the MAIN domain, and is a minor variant of the IP on the current TI K3 SoCs such as AM64x, J721E or J7200 SoCs. The IP is not built with the K3 safety feature in hardware, and has slightly different integration into the overall SoC. Add the support for this IP through a new compatible. Signed-off-by: Suman Anna --- drivers/hwspinlock/omap_hwspinlock.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/hwspinlock/omap_hwspinlock.c b/drivers/hwspinlock/omap_hwspinlock.c index 3b05560456ea..65dbf1ae3aa7 100644 --- a/drivers/hwspinlock/omap_hwspinlock.c +++ b/drivers/hwspinlock/omap_hwspinlock.c @@ -2,11 +2,12 @@ /* * OMAP hardware spinlock driver * - * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2010-2021 Texas Instruments Incorporated - https://www.ti.com * * Contact: Simon Que * Hari Kanigeri * Ohad Ben-Cohen + * Suman Anna */ #include @@ -165,6 +166,7 @@ static int omap_hwspinlock_remove(struct platform_device *pdev) static const struct of_device_id omap_hwspinlock_of_match[] = { { .compatible = "ti,omap4-hwspinlock", }, { .compatible = "ti,am654-hwspinlock", }, + { .compatible = "ti,am64-hwspinlock", }, { /* end */ }, }; MODULE_DEVICE_TABLE(of, omap_hwspinlock_of_match);