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Mon, 08 Feb 2021 12:47:17 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0ACEF100034; Mon, 8 Feb 2021 12:47:17 +0100 (CET) Received: from Webmail-eu.st.com (gpxdag2node6.st.com [10.75.127.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id EDE0B23C7C6; Mon, 8 Feb 2021 12:47:16 +0100 (CET) Received: from localhost (10.75.127.117) by GPXDAG2NODE6.st.com (10.75.127.70) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 8 Feb 2021 12:47:16 +0100 From: Amelie Delaunay To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Alexandre Torgue , Maxime Coquelin Subject: [PATCH v3 1/2] dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property Date: Mon, 8 Feb 2021 12:46:58 +0100 Message-ID: <20210208114659.15269-2-amelie.delaunay@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210208114659.15269-1-amelie.delaunay@foss.st.com> References: <20210208114659.15269-1-amelie.delaunay@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.117] X-ClientProxiedBy: GPXDAG2NODE5.st.com (10.75.127.69) To GPXDAG2NODE6.st.com (10.75.127.70) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.737 definitions=2021-02-08_03:2021-02-08, 2021-02-08 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210208_064725_914418_C671B3AD X-CRM114-Status: GOOD ( 15.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amelie Delaunay , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org usbphyc provides a unique clock called ck_usbo_48m. STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation. ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by: Amelie Delaunay Acked-by: Rob Herring --- Changes in v3: - remove #clock-cells from required properties --- Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml index 46df6786727a..018cc1246ee1 100644 --- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml @@ -51,6 +51,10 @@ properties: vdda1v8-supply: description: regulator providing 1V8 power supply to the PLL block + '#clock-cells': + description: number of clock cells for ck_usbo_48m consumer + const: 0 + #Required child nodes: patternProperties: @@ -120,6 +124,7 @@ examples: vdda1v8-supply = <®18>; #address-cells = <1>; #size-cells = <0>; + #clock-cells = <0>; usbphyc_port0: usb-phy@0 { reg = <0>;