From patchwork Mon Feb 8 14:03:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12075577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E876CC433DB for ; Mon, 8 Feb 2021 14:09:02 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 70B9364D9F for ; Mon, 8 Feb 2021 14:09:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 70B9364D9F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=baikalelectronics.ru Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=lqZAo0D/7LqyW+dzwdY0CdoDI27s6kKW/rPGqrwHN0s=; b=O2FaoYkSjYMKyRoYVJ7PZ2teJ zP0LDsxHg9G24XuVoVF0xqZsIdNHQtl9bMG21uixRMOecmaHcUpZtEw4VuHc4zdjPB3elNPYGSvRN p2rhUKKr4yqdlfpiutlFcnCPZEFpoH5ydEUoPAUFUo9VoMd8W2vTAo7Vq1H4j09K1c5aIFWlzsdcb MYQnRAHr6FuxWjOdzE2mh1V/c7mTWqdEGA6A02pmv91btonOJIsS6vgWKzjw0ge8puzNDSA6PvVoY 7OTb/W5qOh4CKX3hNp9Xi7Qdp7x6xdTLz+X6SoVcZN3mN1PSIYQodo37M8+gKqFKVkF+yyP7TAxjw KIBTxx4eg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l97BE-00049v-DO; Mon, 08 Feb 2021 14:06:24 +0000 Received: from mail.baikalelectronics.com ([87.245.175.226] helo=mail.baikalelectronics.ru) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l978s-00034r-NS for linux-arm-kernel@lists.infradead.org; Mon, 08 Feb 2021 14:04:03 +0000 From: Serge Semin To: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Jakub Kicinski , Joao Pinto , Jose Abreu , Maxime Coquelin Subject: [PATCH 13/20] net: stmmac: Move DMA Tx/Rx init methods to DW MAC lib Date: Mon, 8 Feb 2021 17:03:34 +0300 Message-ID: <20210208140341.9271-14-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20210208140341.9271-1-Sergey.Semin@baikalelectronics.ru> References: <20210208140341.9271-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210208_090355_541100_39E52994 X-CRM114-Status: GOOD ( 11.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Lunn , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Russell King , Serge Semin , Alexey Malahov , Serge Semin , Vyacheslav Mitrofanov , Pavel Parkhomenko , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Heiner Kallweit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org These methods are identical for both DW MAC100 and DW MAC1000 cores, so their implementation can be moved to the common for the core library. Signed-off-by: Serge Semin --- .../ethernet/stmicro/stmmac/dwmac1000_dma.c | 20 ++----------------- .../ethernet/stmicro/stmmac/dwmac100_dma.c | 20 ++----------------- .../net/ethernet/stmicro/stmmac/dwmac_dma.h | 4 ++++ .../net/ethernet/stmicro/stmmac/dwmac_lib.c | 14 +++++++++++++ 4 files changed, 22 insertions(+), 36 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c index 2bac49b49f73..2a04d9d45160 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c @@ -110,22 +110,6 @@ static void dwmac1000_dma_init(void __iomem *ioaddr, writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); } -static void dwmac1000_dma_init_rx(void __iomem *ioaddr, - struct stmmac_dma_cfg *dma_cfg, - dma_addr_t dma_rx_phy, u32 chan) -{ - /* RX descriptor base address list must be written into DMA CSR3 */ - writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR); -} - -static void dwmac1000_dma_init_tx(void __iomem *ioaddr, - struct stmmac_dma_cfg *dma_cfg, - dma_addr_t dma_tx_phy, u32 chan) -{ - /* TX descriptor base address list must be written into DMA CSR4 */ - writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR); -} - static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz) { csr6 &= ~DMA_CONTROL_RFA_MASK; @@ -263,8 +247,8 @@ static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt, const struct stmmac_dma_ops dwmac1000_dma_ops = { .reset = dwmac_dma_reset, .init = dwmac1000_dma_init, - .init_rx_chan = dwmac1000_dma_init_rx, - .init_tx_chan = dwmac1000_dma_init_tx, + .init_rx_chan = dwmac_dma_init_rx, + .init_tx_chan = dwmac_dma_init_tx, .axi = dwmac1000_dma_axi, .dump_regs = dwmac1000_dump_dma_regs, .dma_rx_mode = dwmac1000_dma_operation_mode_rx, diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c index 8f0d9bc7cab5..ad51a7949a42 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c @@ -29,22 +29,6 @@ static void dwmac100_dma_init(void __iomem *ioaddr, writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); } -static void dwmac100_dma_init_rx(void __iomem *ioaddr, - struct stmmac_dma_cfg *dma_cfg, - dma_addr_t dma_rx_phy, u32 chan) -{ - /* RX descriptor base addr lists must be written into DMA CSR3 */ - writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR); -} - -static void dwmac100_dma_init_tx(void __iomem *ioaddr, - struct stmmac_dma_cfg *dma_cfg, - dma_addr_t dma_tx_phy, u32 chan) -{ - /* TX descriptor base addr lists must be written into DMA CSR4 */ - writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR); -} - /* Store and Forward capability is not used at all. * * The transmit threshold can be programmed by setting the TTC bits in the DMA @@ -111,8 +95,8 @@ static void dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x, const struct stmmac_dma_ops dwmac100_dma_ops = { .reset = dwmac_dma_reset, .init = dwmac100_dma_init, - .init_rx_chan = dwmac100_dma_init_rx, - .init_tx_chan = dwmac100_dma_init_tx, + .init_rx_chan = dwmac_dma_init_rx, + .init_tx_chan = dwmac_dma_init_tx, .dump_regs = dwmac100_dump_dma_regs, .dma_tx_mode = dwmac100_dma_operation_mode_tx, .dma_diagnostic_fr = dwmac100_dma_diagnostic_fr, diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h index e5dbd0bc257e..fa919bf75e19 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h @@ -134,8 +134,12 @@ void dwmac_enable_dma_transmission(void __iomem *ioaddr); void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx); void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx); +void dwmac_dma_init_tx(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, + dma_addr_t dma_tx_phy, u32 chan); void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan); void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan); +void dwmac_dma_init_rx(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, + dma_addr_t dma_rx_phy, u32 chan); void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan); void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan); int dwmac_dma_interrupt(void __iomem *ioaddr, struct stmmac_extra_stats *x, diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c index 57a53a600aa5..6ddfc689e77b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c @@ -56,6 +56,13 @@ void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) writel(value, ioaddr + DMA_INTR_ENA); } +void dwmac_dma_init_tx(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, + dma_addr_t dma_tx_phy, u32 chan) +{ + /* TX descriptor base address list must be written into DMA CSR4 */ + writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR); +} + void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) { u32 value = readl(ioaddr + DMA_CONTROL); @@ -70,6 +77,13 @@ void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) writel(value, ioaddr + DMA_CONTROL); } +void dwmac_dma_init_rx(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, + dma_addr_t dma_rx_phy, u32 chan) +{ + /* RX descriptor base address list must be written into DMA CSR3 */ + writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR); +} + void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) { u32 value = readl(ioaddr + DMA_CONTROL);