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IronPort-SDR: MEghTVkivKV3Je28ILO+65t/HQnFIig0VW+On8mMHS/ksVqMTTS5baWlsX0q1B/oHcO8KKN0F3 c5Y3Zmh07SBV3l22hIvm88tBIfEVf1d5ukjGQ8lpchH2Fm/DkgjncEqTZuLXeHpPWwFXMfGWBN 3V/9atKpJcIP2DpgJunsbkQ8P4vjcZHALcht9wU45Mglfqxk7p9mj4XTmi12SugmR4uWTo0l0D BxP1+E0YUMch8QZjysxjv+O7+J+RWpOttHgZDIKzFHqTEXLX2hqPLkVxvmmu112ylLA4ApKfU6 zqA= X-IronPort-AV: E=Sophos;i="5.81,167,1610434800"; d="scan'208";a="108681606" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Feb 2021 02:20:05 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 10 Feb 2021 02:20:04 -0700 Received: from mchp-dev-shegelun.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 10 Feb 2021 02:20:02 -0700 From: Steen Hegelund To: Philipp Zabel , Rob Herring Subject: [PATCH v5 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings Date: Wed, 10 Feb 2021 10:19:50 +0100 Message-ID: <20210210091952.2013027-2-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210210091952.2013027-1-steen.hegelund@microchip.com> References: <20210210091952.2013027-1-steen.hegelund@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210210_042005_803782_B5F44D58 X-CRM114-Status: GOOD ( 12.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Lunn , Alexandre Belloni , devicetree@vger.kernel.org, Steen Hegelund , linux-kernel@vger.kernel.org, Microchip Linux Driver Support , Gregory Clement , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document the Sparx5 reset device driver bindings The driver uses two IO ranges on sparx5 for access to the reset control and the reset status. Signed-off-by: Steen Hegelund --- .../bindings/reset/microchip,rst.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml b/Documentation/devicetree/bindings/reset/microchip,rst.yaml new file mode 100644 index 000000000000..80046172c9f8 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip Sparx5 Switch Reset Controller + +maintainers: + - Steen Hegelund + - Lars Povlsen + +description: | + The Microchip Sparx5 Switch provides reset control and implements the following + functions + - One Time Switch Core Reset (Soft Reset) + +properties: + $nodename: + pattern: "^reset-controller@[0-9a-f]+$" + + compatible: + const: microchip,sparx5-switch-reset + + reg: + items: + - description: cpu block registers + - description: global control block registers + + reg-names: + items: + - const: cpu + - const: gcb + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - reg-names + - "#reset-cells" + +additionalProperties: false + +examples: + - | + reset: reset-controller@0 { + compatible = "microchip,sparx5-switch-reset"; + #reset-cells = <1>; + reg = <0x0 0xd0>, + <0x11010000 0x10000>; + reg-names = "cpu", "gcb"; + }; +