From patchwork Thu Feb 11 17:20:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12083741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1408CC433DB for ; Thu, 11 Feb 2021 17:21:55 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CBFB561493 for ; Thu, 11 Feb 2021 17:21:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CBFB561493 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=bDOzeNJRjukI5cXOIwOG7G9nxM+wp8ysW4GxyT3TnVM=; b=waE03bhseAYnXjMx8ddmoUb1T K64peOVPDSNA3/4HZ0neOfEYRj22kTWP7ObqZTcFwI56Enl23eoSIZBUS1RdzS/BTgBi6bq/9sqkU JY7Z9f7so5Zy6cZHhJxzO7bdFIUkuo+uhlZ/nvMNIM6xo/KDYGIoC04s7EjWlA5mm/qZQ0RIqlllO CCeTJRxaf/+m2IBpZS1jCRmQUgEZX/ID8oJPhbfpPaiR0O7JP09Pfe+7Vy5dF/H28Io0RC7HDoPEw 6eZFTJsjScgy/vEIGEriRiilTDg/2Pk0r6bdszFdeD9766WGm9eI9Y41pfZLjeWKq37jYBfvlexT4 ucip6a8ow==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lAFe8-0002ml-CU; Thu, 11 Feb 2021 17:20:52 +0000 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1lAFe1-0002jW-Ce for linux-arm-kernel@lists.infradead.org; Thu, 11 Feb 2021 17:20:47 +0000 Received: by mail-pl1-x630.google.com with SMTP id u11so3641577plg.13 for ; Thu, 11 Feb 2021 09:20:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SaDNVFpV/oFZvL50IMJ+aksLQj8pFjVfZykazLuHDNY=; b=FhSYnclEl45NUQwZyMCL9KrsTnrrQdPC8N/u6KPWUi7Mhb80cnnl0Sb75wPs3ngQEa 8tZ9X6Vz9jK1+Wr4lVRaHokdr4GIhQK2jQd0hyWBiuMthDHgf2PDcfvLm+bs3+XqTsSj 71VAi/YFpe7xcpFXIJEgaXix5rSVTEHkuGSToFdsU9lc+RRMwx6r9p5pMMYQqs+fHdTq RJUvCjvBZNIqHXQiObfsm9Z9A/wg5z8GM3XwlGJVxg84nfhrzUlyQGyf9nouxWVZj9ff FHPdninbRM/p6qQ0zWixnGQ8J2O3RvOzznKJcnQW4r7MxhC41DJmHgSbUapgHpGPzNEO igsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SaDNVFpV/oFZvL50IMJ+aksLQj8pFjVfZykazLuHDNY=; b=aImbnfRPAC/pyqZOUWVqqyvj50hdnmsKJRyMlns09GYD4ht5oFMyfcvenWvcgOJ0Xc am4RbsujTnuCPXIWLOjX6k4XPtYk+HwhmIrfOjNZUfLBk0wkQA3oLAHRRYbyMnewq661 a0Vezjwn0V9HNGrku+lGQrFs7jr3TuP+2SMGj4G6okH/ddjrSPie2cHg2VYTaeqiqGBO bLL+PMDkIjMyzKRotDsEwLkbXFiAx/BgOZR05zQfs8MrSq8+8pO3NunolgPlMsHqzSoK D6U/BFE69HoSkdyv7os/vODf03c2zbUb1JiVZB5L6Z7Yv1xaxlCxmMk+b5gP7SXnQwNP vtjw== X-Gm-Message-State: AOAM533iP7wYHRs+TGQ2iwMKD5KZSNbdCsBAJhXx2Y/OrMh0/gQrlg9N hH2wWJaZCSHgy5hG3gF1GcWRfA== X-Google-Smtp-Source: ABdhPJx9AyXjl0xrq1EZG664/xo5G+Uack/Ewln/jfeLWEPzUBZLYtHIKPjUN8vEdennJGsaUVBNvg== X-Received: by 2002:a17:903:1d0:b029:df:d098:f1cb with SMTP id e16-20020a17090301d0b02900dfd098f1cbmr8480698plh.49.1613064042909; Thu, 11 Feb 2021 09:20:42 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e15sm7415384pgr.81.2021.02.11.09.20.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Feb 2021 09:20:41 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH v2 1/3] coresight: etm-perf: Clarify comment on perf options Date: Thu, 11 Feb 2021 10:20:36 -0700 Message-Id: <20210211172038.2483517-2-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210211172038.2483517-1-mathieu.poirier@linaro.org> References: <20210211172038.2483517-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210211_122045_455641_A18FB232 X-CRM114-Status: GOOD ( 17.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Leo Yan In theory, the options should be arbitrary values and are neutral for any ETM version; so far perf tool uses ETMv3.5/PTM ETMCR config bits except for register's bit definitions, also uses as options. This can introduce confusion, especially if we want to add a new option but the new option is not supported by ETMv3.5/PTM ETMCR. But on the other hand, we cannot change options since these options are generic CoreSight PMU ABI. For easier maintenance and avoid confusion, this patch refines the comment to clarify perf options, and gives out the background info for these bits are coming from ETMv3.5/PTM. Afterwards, we should take these options as general knobs, and if there have any confliction with ETMv3.5/PTM, should consider to define saperate macros for ETMv3.5/PTM ETMCR config bits. Suggested-by: Suzuki K Poulose Signed-off-by: Leo Yan Reviewed-by: Suzuki K Poulose Message-Id: <20210206150833.42120-2-leo.yan@linaro.org> Signed-off-by: Mathieu Poirier --- .../hwtracing/coresight/coresight-etm-perf.c | 5 ++++- include/linux/coresight-pmu.h | 17 ++++++++++++----- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index bdc34ca449f7..465ef1aa8c82 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -27,7 +27,10 @@ static bool etm_perf_up; static DEFINE_PER_CPU(struct perf_output_handle, ctx_handle); static DEFINE_PER_CPU(struct coresight_device *, csdev_src); -/* ETMv3.5/PTM's ETMCR is 'config' */ +/* + * The PMU formats were orignally for ETMv3.5/PTM's ETMCR 'config'; + * now take them as general formats and apply on all ETMs. + */ PMU_FORMAT_ATTR(cycacc, "config:" __stringify(ETM_OPT_CYCACC)); PMU_FORMAT_ATTR(contextid, "config:" __stringify(ETM_OPT_CTXTID)); PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS)); diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index b0e35eec6499..5dc47cfdcf07 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -10,11 +10,18 @@ #define CORESIGHT_ETM_PMU_NAME "cs_etm" #define CORESIGHT_ETM_PMU_SEED 0x10 -/* ETMv3.5/PTM's ETMCR config bit */ -#define ETM_OPT_CYCACC 12 -#define ETM_OPT_CTXTID 14 -#define ETM_OPT_TS 28 -#define ETM_OPT_RETSTK 29 +/* + * Below are the definition of bit offsets for perf option, and works as + * arbitrary values for all ETM versions. + * + * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, + * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and + * directly use below macros as config bits. + */ +#define ETM_OPT_CYCACC 12 +#define ETM_OPT_CTXTID 14 +#define ETM_OPT_TS 28 +#define ETM_OPT_RETSTK 29 /* ETMv4 CONFIGR programming bits for the ETM OPTs */ #define ETM4_CFG_BIT_CYCACC 4