From patchwork Wed Mar 3 08:11:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steen Hegelund X-Patchwork-Id: 12113661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-21.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB4A0C433E0 for ; Wed, 3 Mar 2021 15:11:31 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 40EFE64EEC for ; Wed, 3 Mar 2021 15:11:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 40EFE64EEC Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3TlkhVPxVHuNhreyfUVFookP4/b4GlSes6X/ZwwLDVA=; b=BdJFexwDiklqg/Q1oA+Hon9ix E9wLpNM+qp7JKmQmpY7ELBA0pe7mm43AEdtOx3KG6pOUUfcmahXOy8C79T3mgJthl86R6G3nWkqNH AS4FBKJv7wp+6Dt84oMi5F5CLAOtMLNJqv3WwYWZYF8nJDmqhFyOzMoIuiwWef/g2lVe2MPwz4VHJ XG0MSGMrdT9O/WM8N117+yOeUA4o+rq/ydCnKx0V1usWF0nvZR0Ra+LXmZlP5XOQl15bP0eJW3f82 iM2gd48oMyQkUZv/vokk4vfdjzsgUVQivU/Hn4DJgELNAOkQ51CPMoelEtwmY2CZB77BpIZ6rK8ZW Ll8UvaOfw==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lHT7S-005JPA-1Q; Wed, 03 Mar 2021 15:08:58 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lHSC0-0054bN-8u for linux-arm-kernel@desiato.infradead.org; Wed, 03 Mar 2021 14:09:36 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Type:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From:Sender :Reply-To:Content-ID:Content-Description; bh=Wpxo/gbAfSnboVqkCv2myNFkmbJ9fa9KYQ1nm7xClqw=; b=Hk4faIsd9i8d9c1ZUug2FNUEg5 2IY6/MNvHpOByEAQN80m6MB7eTW5AAvnLnmv3GF8arHM/eOlgFLAPMnQGKjXEz7T3KkXwUmrgIvy0 dDw1WWP+v33S4m3OH56G3S6G0ChGFeb9g0A04CfGPFkcb1nPMyONIpjnslrQn6NMKWiXJdopm0TwM YS4S74SdWNTlSqgC0R10/YoCgsmJ9lOie2+XaTg65oksAgsXlN9hDGDYagLmS0Xda5He3nEBF/cZT L+lAUyXsD72C8RwflxIR60vcYQzEN0FLFrZtMGpzMzRxY0ZaJIXxksXxBeZJpYMFRBeQi3aOC86vx wGuKFtUw==; Received: from esa.microchip.iphmx.com ([68.232.154.123]) by casper.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lHMdE-001npT-0l for linux-arm-kernel@lists.infradead.org; Wed, 03 Mar 2021 08:13:20 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1614759200; x=1646295200; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SgtkHUhk7AyV98FfTKFu+O0lqqTdsBUVkl0kwM8nzAY=; b=mUHkPGd98MLFgmAGj2BnosDp61is6f2gNR9k7FSpB71GHHI17wpuJlyO Axynt5ZlZjtuJ5uOUId+SOmhSiYAAnoh2Npc8hktklH+lFq5zmYcGUlNV ZEe4S8EGrmmTFjH7rAHdz6XqN1RGohzIyzUX8w38YVdWN9MebQx/8LGX4 n+yH3RNy7oDjqga+pB7XYxzwZ/kp+Kl1NP2U5u691BfNVjWjt/ZeYuAAW JiaIuPhHhz1QlcnAem5zCW42ptSk3yiSMcigQW3OZIg3eVgitM+hm2OGn UdNJkxEaO/ZTLlA3iRvsstq10Ul4kn7RVoiubcGMoDN5NBTHzY6GJZdgZ A==; IronPort-SDR: mba0H4FvJvIu8NE0pTR3/xflqSwf2acdcRhh26088ezk1Br6K2auOcHUWm7rAI+VWYyot+wtJf OehdlOZjoGKEKoha0clQRPC0Jg5A9en+4Xeeqo6fKqSwpjwjRsTldSn3b69LYI7B1dZIt0HsBN 7NRr6wpeFLnv4CUau+Ly+EOTTqBEjUiTbSRI+hlcuBzijK5Ini1+BKN98IIMX3rzeGUTe/wBQb v1pHSMm1E+TyLWjP26RfIDRZNedsqsVr14mH8jeTfrJVvd/+CIlYKnya68xxaCwfdxcn/F9AG5 /uo= X-IronPort-AV: E=Sophos;i="5.81,219,1610434800"; d="scan'208";a="105779113" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Mar 2021 01:12:14 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Wed, 3 Mar 2021 01:12:09 -0700 Received: from mchp-dev-shegelun.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Wed, 3 Mar 2021 01:12:07 -0700 From: Steen Hegelund To: Philipp Zabel CC: Steen Hegelund , Andrew Lunn , Microchip Linux Driver Support , Alexandre Belloni , Gregory Clement , , Subject: [PATCH v7 2/3] reset: mchp: sparx5: add switch reset driver Date: Wed, 3 Mar 2021 09:11:57 +0100 Message-ID: <20210303081158.684532-3-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210303081158.684532-1-steen.hegelund@microchip.com> References: <20210303081158.684532-1-steen.hegelund@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210303_081320_566268_9656D1DD X-CRM114-Status: GOOD ( 20.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Sparx5 Switch SoC has a number of components that can be reset indiviually, but at least the Switch Core needs to be in a well defined state at power on, when any of the Sparx5 drivers starts to access the Switch Core, this reset driver is available. The reset driver is loaded early via the postcore_initcall interface, and will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc) that are loaded next, and the first of them to be loaded can perform the one-time Switch Core reset that is needed. The driver has protection so that the system busses, DDR controller, PCI-E and ARM A53 CPU and a few other subsystems are not touched by the reset. Signed-off-by: Steen Hegelund Reviewed-by: Alexandre Belloni --- drivers/reset/Kconfig | 8 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-microchip-sparx5.c | 146 +++++++++++++++++++++++++ 3 files changed, 155 insertions(+) create mode 100644 drivers/reset/reset-microchip-sparx5.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 4171c6f76385..c26798092ccf 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -111,6 +111,14 @@ config RESET_LPC18XX help This enables the reset controller driver for NXP LPC18xx/43xx SoCs. +config RESET_MCHP_SPARX5 + bool "Microchip Sparx5 reset driver" + depends on HAS_IOMEM || COMPILE_TEST + default y if SPARX5_SWITCH + select MFD_SYSCON + help + This driver supports switch core reset for the Microchip Sparx5 SoC. + config RESET_MESON tristate "Meson Reset Driver" depends on ARCH_MESON || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 65a118a91b27..c1d6aa9b1b52 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o obj-$(CONFIG_RESET_K210) += reset-k210.o obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o +obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o obj-$(CONFIG_RESET_NPCM) += reset-npcm.o diff --git a/drivers/reset/reset-microchip-sparx5.c b/drivers/reset/reset-microchip-sparx5.c new file mode 100644 index 000000000000..cff39a643a14 --- /dev/null +++ b/drivers/reset/reset-microchip-sparx5.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Microchip Sparx5 Switch Reset driver + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * The Sparx5 Chip Register Model can be browsed at this location: + * https://github.com/microchip-ung/sparx-5_reginfo + */ +#include +#include +#include +#include +#include +#include + +#define PROTECT_REG 0x84 +#define PROTECT_BIT BIT(10) +#define SOFT_RESET_REG 0x00 +#define SOFT_RESET_BIT BIT(1) + +struct mchp_reset_context { + struct regmap *cpu_ctrl; + struct regmap *gcb_ctrl; + struct reset_controller_dev rcdev; +}; + +static struct regmap_config sparx5_reset_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static int sparx5_switch_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mchp_reset_context *ctx = + container_of(rcdev, struct mchp_reset_context, rcdev); + u32 val; + + /* Make sure the core is PROTECTED from reset */ + regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT, PROTECT_BIT); + + /* Start soft reset */ + regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT); + + /* Wait for soft reset done */ + return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val, + (val & SOFT_RESET_BIT) == 0, + 1, 100); +} + +static const struct reset_control_ops sparx5_reset_ops = { + .reset = sparx5_switch_reset, +}; + +static int mchp_sparx5_map_syscon(struct platform_device *pdev, char *name, + struct regmap **target) +{ + struct device_node *syscon_np; + struct regmap *regmap; + int err; + + syscon_np = of_parse_phandle(pdev->dev.of_node, name, 0); + if (!syscon_np) + return -ENODEV; + regmap = syscon_node_to_regmap(syscon_np); + of_node_put(syscon_np); + if (IS_ERR(regmap)) { + err = PTR_ERR(regmap); + dev_err(&pdev->dev, "No '%s' map: %d\n", name, err); + return err; + } + *target = regmap; + return 0; +} + +static int mchp_sparx5_map_io(struct platform_device *pdev, int index, + struct regmap **target) +{ + struct resource *res; + struct regmap *map; + void __iomem *mem; + + mem = devm_platform_get_and_ioremap_resource(pdev, index, &res); + if (!mem) { + dev_err(&pdev->dev, "Could not map resource %d\n", index); + return -ENXIO; + } + sparx5_reset_regmap_config.name = res->name; + map = devm_regmap_init_mmio(&pdev->dev, mem, &sparx5_reset_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); + *target = map; + return 0; +} + +static int mchp_sparx5_reset_probe(struct platform_device *pdev) +{ + struct device_node *dn = pdev->dev.of_node; + struct mchp_reset_context *ctx; + int err; + + ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + err = mchp_sparx5_map_syscon(pdev, "cpu-syscon", &ctx->cpu_ctrl); + if (err) + return err; + err = mchp_sparx5_map_io(pdev, 0, &ctx->gcb_ctrl); + if (err) + return err; + + ctx->rcdev.owner = THIS_MODULE; + ctx->rcdev.nr_resets = 1; + ctx->rcdev.ops = &sparx5_reset_ops; + ctx->rcdev.of_node = dn; + + return devm_reset_controller_register(&pdev->dev, &ctx->rcdev); +} + +static const struct of_device_id mchp_sparx5_reset_of_match[] = { + { + .compatible = "microchip,sparx5-switch-reset", + }, + { } +}; + +static struct platform_driver mchp_sparx5_reset_driver = { + .probe = mchp_sparx5_reset_probe, + .driver = { + .name = "sparx5-switch-reset", + .of_match_table = mchp_sparx5_reset_of_match, + }, +}; + +static int __init mchp_sparx5_reset_init(void) +{ + return platform_driver_register(&mchp_sparx5_reset_driver); +} + +postcore_initcall(mchp_sparx5_reset_init); + +MODULE_DESCRIPTION("Microchip Sparx5 switch reset driver"); +MODULE_AUTHOR("Steen Hegelund "); +MODULE_LICENSE("Dual MIT/GPL");