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Wed, 03 Mar 2021 09:05:59 -0800 (PST) X-Google-Smtp-Source: ABdhPJy/w4VEMRsiBT75nmEd1w/T3n9ICG9GjGPK8ANFaXpMFx0mRKUTD31eTCQcfxUG5OuVGBVtuA== X-Received: by 2002:a1c:1d82:: with SMTP id d124mr13175wmd.1.1614791147050; Wed, 03 Mar 2021 09:05:47 -0800 (PST) Received: from redfedo.redhat.com ([2a01:cb14:499:3d00:cd47:f651:9d80:157a]) by smtp.gmail.com with ESMTPSA id d29sm32957827wra.51.2021.03.03.09.05.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 09:05:46 -0800 (PST) From: Julien Thierry To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, broonie@kernel.org, ycote@redhat.com, Julien Thierry Subject: [RFC PATCH v2 3/8] arm64: insn: Reduce header dependencies of instruction decoder Date: Wed, 3 Mar 2021 18:05:31 +0100 Message-Id: <20210303170536.1838032-4-jthierry@redhat.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20210303170536.1838032-1-jthierry@redhat.com> References: <20210303170536.1838032-1-jthierry@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=jthierry@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The instruction encoder/decoder depends on alternative headers only for single macro definitions that could be part of the instruction decoder. Signed-off-by: Julien Thierry --- arch/arm64/include/asm/alternative-macros.h | 3 --- arch/arm64/include/asm/insn.h | 3 ++- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/alternative-macros.h b/arch/arm64/include/asm/alternative-macros.h index 5df500dcc627..c01edf4d988d 100644 --- a/arch/arm64/include/asm/alternative-macros.h +++ b/arch/arm64/include/asm/alternative-macros.h @@ -6,9 +6,6 @@ #define ARM64_CB_PATCH ARM64_NCAPS -/* A64 instructions are always 32 bits. */ -#define AARCH64_INSN_SIZE 4 - #ifndef __ASSEMBLY__ #include diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index 14aa2f3aebfe..ffcdeac80026 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -10,7 +10,8 @@ #include #include -#include +/* A64 instructions are always 32 bits. */ +#define AARCH64_INSN_SIZE 4 #ifndef __ASSEMBLY__ /*