| Message ID | 20210311020954.842341-1-ilya.lipnitskiy@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [net-next,v2,1/3] net: dsa: mt7530: setup core clock even in TRGMII mode | expand |
On Wed, Mar 10, 2021 at 06:09:52PM -0800, Ilya Lipnitskiy wrote: > A recent change to MIPS ralink reset logic made it so mt7530 actually > resets the switch on platforms such as mt7621 (where bit 2 is the reset > line for the switch). That exposed an issue where the switch would not > function properly in TRGMII mode after a reset. > > Reconfigure core clock in TRGMII mode to fix the issue. > > Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled. Please don't submit the same patch to net and net-next. Anything which is accepted into net, will get merged into net-next about a week later. If your other two patches depend on this patch, you need to wait for the merge to happen, then submit them. Andrew
On Wed, Mar 10, 2021 at 06:09:52PM -0800, Ilya Lipnitskiy wrote: > A recent change to MIPS ralink reset logic made it so mt7530 actually > resets the switch on platforms such as mt7621 (where bit 2 is the reset > line for the switch). That exposed an issue where the switch would not > function properly in TRGMII mode after a reset. > > Reconfigure core clock in TRGMII mode to fix the issue. Hi Ilya For a patch series, netdev expects there to be a patch 0/X which explains the big picture. What do these patches as a whole do. This then gets used in the merge commit message. Andrew
On Thu, Mar 11, 2021 at 9:41 AM Andrew Lunn <andrew@lunn.ch> wrote: > > On Wed, Mar 10, 2021 at 06:09:52PM -0800, Ilya Lipnitskiy wrote: > > A recent change to MIPS ralink reset logic made it so mt7530 actually > > resets the switch on platforms such as mt7621 (where bit 2 is the reset > > line for the switch). That exposed an issue where the switch would not > > function properly in TRGMII mode after a reset. > > > > Reconfigure core clock in TRGMII mode to fix the issue. > > > > Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled. > > Please don't submit the same patch to net and net-next. Anything > which is accepted into net, will get merged into net-next about a week > later. If your other two patches depend on this patch, you need to > wait for the merge to happen, then submit them. I don't mind waiting, but it's been more than a week now. When is the next merge of net-next into net planned to happen? Ilya
On Tue, Mar 23, 2021 at 6:33 PM Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> wrote: > > On Thu, Mar 11, 2021 at 9:41 AM Andrew Lunn <andrew@lunn.ch> wrote: > > > > On Wed, Mar 10, 2021 at 06:09:52PM -0800, Ilya Lipnitskiy wrote: > > > A recent change to MIPS ralink reset logic made it so mt7530 actually > > > resets the switch on platforms such as mt7621 (where bit 2 is the reset > > > line for the switch). That exposed an issue where the switch would not > > > function properly in TRGMII mode after a reset. > > > > > > Reconfigure core clock in TRGMII mode to fix the issue. > > > > > > Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled. > > > > Please don't submit the same patch to net and net-next. Anything > > which is accepted into net, will get merged into net-next about a week > > later. If your other two patches depend on this patch, you need to > > wait for the merge to happen, then submit them. > I don't mind waiting, but it's been more than a week now. When is the > next merge of net-next into net planned to happen? Oops, I meant net into net-next... Ilya
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index f06f5fa2f898..9871d7cff93a 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -436,34 +436,32 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) TD_DM_DRVP(8) | TD_DM_DRVN(8)); /* Setup core clock for MT7530 */ - if (!trgint) { - /* Disable MT7530 core clock */ - core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); - - /* Disable PLL, since phy_device has not yet been created - * provided for phy_[read,write]_mmd_indirect is called, we - * provide our own core_write_mmd_indirect to complete this - * function. - */ - core_write_mmd_indirect(priv, - CORE_GSWPLL_GRP1, - MDIO_MMD_VEND2, - 0); - - /* Set core clock into 500Mhz */ - core_write(priv, CORE_GSWPLL_GRP2, - RG_GSWPLL_POSDIV_500M(1) | - RG_GSWPLL_FBKDIV_500M(25)); + /* Disable MT7530 core clock */ + core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); - /* Enable PLL */ - core_write(priv, CORE_GSWPLL_GRP1, - RG_GSWPLL_EN_PRE | - RG_GSWPLL_POSDIV_200M(2) | - RG_GSWPLL_FBKDIV_200M(32)); - - /* Enable MT7530 core clock */ - core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); - } + /* Disable PLL, since phy_device has not yet been created + * provided for phy_[read,write]_mmd_indirect is called, we + * provide our own core_write_mmd_indirect to complete this + * function. + */ + core_write_mmd_indirect(priv, + CORE_GSWPLL_GRP1, + MDIO_MMD_VEND2, + 0); + + /* Set core clock into 500Mhz */ + core_write(priv, CORE_GSWPLL_GRP2, + RG_GSWPLL_POSDIV_500M(1) | + RG_GSWPLL_FBKDIV_500M(25)); + + /* Enable PLL */ + core_write(priv, CORE_GSWPLL_GRP1, + RG_GSWPLL_EN_PRE | + RG_GSWPLL_POSDIV_200M(2) | + RG_GSWPLL_FBKDIV_200M(32)); + + /* Enable MT7530 core clock */ + core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); /* Setup the MT7530 TRGMII Tx Clock */ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
A recent change to MIPS ralink reset logic made it so mt7530 actually resets the switch on platforms such as mt7621 (where bit 2 is the reset line for the switch). That exposed an issue where the switch would not function properly in TRGMII mode after a reset. Reconfigure core clock in TRGMII mode to fix the issue. Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled. Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines") Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> --- drivers/net/dsa/mt7530.c | 52 +++++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 27 deletions(-)