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IronPort-SDR: cPYFzHQH/xRbNznlMbvR00a9jgdOzuouB3dWYtHCEGiGh6Dhnj5/OIiOZuqokhrCvMGmEQNgsV M/QssLNFjsaNym+nfKMhuxToefhDNmpLFxDRjV0tEKckaWPYOujihiVTWq38ydm08OtNX/hWx6 Px0FAlh7ytlQDoBMDSzek+1NOVTFuabUi5oqskz0Yp+c5+q5sRvo7AoCLpebJ0IuQ3h453zsWJ zqPz2H5GiB+PuBQWmvFUGZCUSj2IwUNLTEaXl5TEZC4H2j3EZ0JvLrAc9UGdVO6FcFaGuGIa4T xtA= X-IronPort-AV: E=Sophos;i="5.81,251,1610434800"; d="scan'208";a="47683728" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Mar 2021 02:08:56 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 16 Mar 2021 02:08:56 -0700 Received: from mchp-dev-shegelun.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Tue, 16 Mar 2021 02:08:54 -0700 From: Steen Hegelund To: Philipp Zabel , Rob Herring CC: Steen Hegelund , Andrew Lunn , Microchip Linux Driver Support , Alexandre Belloni , Gregory Clement , , , Subject: [PATCH v8 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver Date: Tue, 16 Mar 2021 10:08:39 +0100 Message-ID: <20210316090839.3207930-4-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210316090839.3207930-1-steen.hegelund@microchip.com> References: <20210316090839.3207930-1-steen.hegelund@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210316_090859_226017_DA538498 X-CRM114-Status: GOOD ( 10.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This provides reset driver support for the Microchip Sparx5 PCB134 and PCB135 reference boards. The Sparx5 Switch will no longer use the Ocelot Chip Reset Driver (with the compatible string "microchip,sparx5-chip-reset"), but use a separate driver that exposes a reset controller interface and has the compatiple string "microchip,sparx5-switch-reset". Eventually the Sparx5 reset support will be removed from the Ocelot chip reset driver. Signed-off-by: Steen Hegelund Reviewed-by: Alexandre Belloni --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 380281f312d8..dc3ada5cf9fc 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -132,9 +132,12 @@ mux: mux-controller { }; }; - reset@611010008 { - compatible = "microchip,sparx5-chip-reset"; + reset: reset-controller@611010008 { + compatible = "microchip,sparx5-switch-reset"; reg = <0x6 0x11010008 0x4>; + reg-names = "gcb"; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; }; uart0: serial@600100000 {