diff mbox series

[4/5] arm64: dts: mediatek: mt8167: add iommu node

Message ID 20210405200821.2203458-4-fparent@baylibre.com (mailing list archive)
State New, archived
Headers show
Series [1/5] arm64: dts: mediatek: mt8167: add mmsys node | expand

Commit Message

Fabien Parent April 5, 2021, 8:08 p.m. UTC 
Add node for the MT8167's IOMMU.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 arch/arm64/boot/dts/mediatek/mt8167.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Yong Wu (吴勇) April 6, 2021, 8:41 a.m. UTC | #1 
On Mon, 2021-04-05 at 22:08 +0200, Fabien Parent wrote:
> Add node for the MT8167's IOMMU.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8167.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> index 9b352031c5f6..3ba03ca749b2 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> @@ -173,5 +173,14 @@ larb2: larb@16010000 {
>  			clock-names = "apb", "smi";
>  			power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
>  		};
> +
> +		iommu: m4u@10203000 {
> +			cell-index = <0>;

Remove this line.

> +			compatible = "mediatek,mt8167-m4u";
> +			reg = <0 0x10203000 0 0x1000>;
> +			mediatek,larbs = <&larb0 &larb1 &larb2>;
> +			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
> +			#iommu-cells = <1>;
> +		};
>  	};
>  };
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index 9b352031c5f6..3ba03ca749b2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
@@ -173,5 +173,14 @@  larb2: larb@16010000 {
 			clock-names = "apb", "smi";
 			power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
 		};
+
+		iommu: m4u@10203000 {
+			cell-index = <0>;
+			compatible = "mediatek,mt8167-m4u";
+			reg = <0 0x10203000 0 0x1000>;
+			mediatek,larbs = <&larb0 &larb1 &larb2>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
+			#iommu-cells = <1>;
+		};
 	};
 };