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bh=Qp1rtf5vTNCYxLgq97ox1ro8HilwNvlQ34tjmWDteno=; b=rfXxO5sGRCWRlK5R7p4Gwv5nyYx0uBm7A1SpYOn8DFJC5cj6/HGqbVMBnkFL29fbSF RUEKLwun5y7ZW+CmElfiQh5jcz5EIMkEqL2nJ4r7Hcg0kfwUzXe1W7fyAsSaop9sRKnz Fje/WG2ma3Yq6O6lnmRpWCg26+y2auaOI01wYOTbVjGtzyrP5kivygxD6nrAPiwgdQTM aEUqwA1vJ5w4J6ImvFd2OehFSzER66HW1qgyTuFvBCCCHmZnvo30c5mhRgm4jvzh/Whf cHu4bp3D9OrdzK6P3h8QkNdHXtfUsNwzaqZ4HJI0QuNXsS7eP5EsKQHedmAW3pYorFvJ 3FVw== X-Gm-Message-State: AOAM532LRHT61DMzdiwYIvl9jLsjkDtpYt2yAfmzkuiP5lopfoJ8HsPv UZoxEtt86pXjv/ApX/4BEwSbP4TnO1VA8Q== X-Google-Smtp-Source: ABdhPJwq1IQoqE7/mmybFnQ9IpYRleea4gq55kbZKh4LVZhLh5cQ9efS2H/C4DTU95M15AYAxU+IMA== X-Received: by 2002:adf:fdca:: with SMTP id i10mr23520500wrs.55.1618427951061; Wed, 14 Apr 2021 12:19:11 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:546d:7d59:1703:bf96]) by smtp.gmail.com with ESMTPSA id a3sm327073wru.40.2021.04.14.12.19.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Apr 2021 12:19:10 -0700 (PDT) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, linux-doc@vger.kernel.org, suzuki.poulose@arm.com Cc: yabinc@google.com, corbet@lwn.net, leo.yan@linaro.org, alexander.shishkin@linux.intel.com, tingwei@codeaurora.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, Mike Leach Subject: [PATCH v7 06/10] coresight: etm-perf: Update to activate selected configuration Date: Wed, 14 Apr 2021 20:18:59 +0100 Message-Id: <20210414191903.18349-7-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210414191903.18349-1-mike.leach@linaro.org> References: <20210414191903.18349-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210414_121912_891693_178D2A78 X-CRM114-Status: GOOD ( 17.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add calls to activate the selected configuration as perf starts and stops the tracing session. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose Reviewed-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm-perf.c | 14 +++++++++++++- drivers/hwtracing/coresight/coresight-etm-perf.h | 2 ++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 26b4bca156aa..560baefdfed8 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -215,6 +215,10 @@ static void free_event_data(struct work_struct *work) /* Free the sink buffers, if there are any */ free_sink_buffer(event_data); + /* clear any configuration we were using */ + if (event_data->cfg_hash) + cscfg_deactivate_config(event_data->cfg_hash); + for_each_cpu(cpu, mask) { struct list_head **ppath; @@ -292,7 +296,7 @@ static bool sinks_compatible(struct coresight_device *a, static void *etm_setup_aux(struct perf_event *event, void **pages, int nr_pages, bool overwrite) { - u32 id; + u32 id, cfg_hash; int cpu = event->cpu; cpumask_t *mask; struct coresight_device *sink = NULL; @@ -310,6 +314,14 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, sink = user_sink = coresight_get_sink_by_id(id); } + /* check if user wants a coresight configuration selected */ + cfg_hash = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32); + if (cfg_hash) { + if (cscfg_activate_config(cfg_hash)) + goto err; + event_data->cfg_hash = cfg_hash; + } + mask = &event_data->mask; /* diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h index ba617fe2217e..468f7799ab4f 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.h +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h @@ -49,12 +49,14 @@ struct etm_filters { * @work: Handle to free allocated memory outside IRQ context. * @mask: Hold the CPU(s) this event was set for. * @snk_config: The sink configuration. + * @cfg_hash: The hash id of any coresight config selected. * @path: An array of path, each slot for one CPU. */ struct etm_event_data { struct work_struct work; cpumask_t mask; void *snk_config; + u32 cfg_hash; struct list_head * __percpu *path; };