From patchwork Fri Apr 16 08:40:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steen Hegelund X-Patchwork-Id: 12207185 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1758C43460 for ; Fri, 16 Apr 2021 09:08:03 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3E8876113B for ; Fri, 16 Apr 2021 09:08:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3E8876113B Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=IaQCxJR06dLJ3jXmfzx5rWNtTqDyIXnkZlRB2r6Bb+8=; b=W2cDlqdF7bgn2GJXbBCoZ6R2G kL7Pr3KTABSrfQs3lOwKJ3Nk3yR085aVlht94XHU4WFYhfyO/4wlpjh7yMT9lwkU2U9ESH8lR6c/R 2nXbgKj79t8Yoe7tSh+RlNBB04OZE+Bz/8snh7g3wYoEFd22ZOubXR3JVCHUlTkpEK9uDLXcEikWQ OouYESmm6QyqO1cFrU7Yiu0V9FAEp+PZ7f7D7g4diGZyqqgf+BgJLBc4cDIPh8x4rWZbNMCTuWaHt +BE5J367lCPnEgLWjX6WlSspgBvQG7t1ocN+bZK7HdsH3Nw6Yegeyabo1iMRJctmhOwgOQHn0nmfc LEzIKXikA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lXKPD-001TVb-S7; Fri, 16 Apr 2021 09:04:52 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lXK2F-001Ors-Pq for linux-arm-kernel@desiato.infradead.org; Fri, 16 Apr 2021 08:41:07 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Sender:Reply-To:Content-ID:Content-Description; bh=U4ByfyZNnCMaaz248hsFxEKlDW0bN4CezVYV49f+IAE=; b=vFgsE31JQjyMOyPA5QKVfhSOVW rTiKWLM6oXXJFKRWCJmjM4C15XFZ40LwZlCxTEjnxD/W/bYZ7AdJ1nBmggLPtDw3EntsZAeFP0rmy ICkk2D6KF/FFHOpmNyssgi3Cr4Fn93PEljBb7ZI44aOeMvRZUk88pKiIzL/JuUwYIE2G8xuEXQHsn 0edUtYLYimKV41lCi5n1yeR2Sytws1TxsuMy1AEGvU5YsOUxnjRh2EhYMqGWEXhVOVxBpekgvOwTE v+kug8di9NCMzQvhhaCZFFIiYQEIqqc2KLA/p5MV/SZFykx/cf+iI81oUyx4LKvMUOxh3H1tYto0m ZbWfvwIg==; Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lXK2C-009Cep-Vw for linux-arm-kernel@lists.infradead.org; Fri, 16 Apr 2021 08:41:06 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1618562465; x=1650098465; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8lTZOjpt/PsZ0L6mL9vuEq3HADt4pfMakp+8pxOPEJk=; b=TOy9FXivYb7/9jlatQOqNK8podR9qdWJRkPKWxOJKWG5Nj0Wbk3l0jUc W+ZtyZL3FPJ5b5WVSpWzmN+6ejlsfPYbKduAuw0lYGjldIONUhgR39hme CUiigYGZz2+gmUW2QEliTWiGuXrZ2834wwMFaNmjgkkuYd3AZq1kV1wCH FOXD3vF8uKnm9/dNjwwFmifiSGeklEzmEGf5IuV8Ew8qzjPeBCn4eOp/9 D1oX4mJgv619brn1zPNvXisx7siyPRs8pieleUo8Dk1eahsPFjNjzCEp6 8vyBFZ1myqjkYBLs1NphunRdAvLHdc9Db8KURuLEudiNUNmGtJnKp87px g==; IronPort-SDR: Ha6NQ0j0CyD2wsaq7XsdO2Euv7+sh+eBpsXlZ5y52Mx46fmY+ed1kesyLwx2NelqvkM/NxS1E5 RgAWy0HfIdM9ErtRcbk6MB3H++4cREZE7mkVSlisjsA6x49BYSHDjo2jQt8GAWHWDe2WYITkwp Oy/GOPAqlDHBFObS8LGAssse1rV8N9vexGmGf9RC2yM37FIicaoNfMtiyQSAc0GqCO7ocWG044 7/MTFtgT0y48H4pQCEkiIP1SYuwK40lIutn1H8MRJYeiCEFH5xkhv9ZfVF/y2LPeF1914XgLZ9 b5w= X-IronPort-AV: E=Sophos;i="5.82,226,1613458800"; d="scan'208";a="116692462" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Apr 2021 01:41:02 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Fri, 16 Apr 2021 01:41:01 -0700 Received: from mchp-dev-shegelun.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Fri, 16 Apr 2021 01:40:59 -0700 From: Steen Hegelund To: Philipp Zabel , Rob Herring CC: Steen Hegelund , Andrew Lunn , Microchip Linux Driver Support , Alexandre Belloni , Gregory Clement , , , , "Rob Herring" Subject: [PATCH v9 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings Date: Fri, 16 Apr 2021 10:40:52 +0200 Message-ID: <20210416084054.2922327-2-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210416084054.2922327-1-steen.hegelund@microchip.com> References: <20210416084054.2922327-1-steen.hegelund@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210416_014105_062672_E761BC7A X-CRM114-Status: GOOD ( 12.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document the Sparx5 reset device driver bindings The driver uses a syscon and an IO range on sparx5 for access to the reset control and the reset status. Sparx5 will no longer use the existing Ocelot chip reset driver, but use this new switch reset driver as it has the reset controller interface that allows the first client to perform the reset on behalf of all the Sparx5 component drivers. Signed-off-by: Steen Hegelund Reviewed-by: Rob Herring --- .../bindings/reset/microchip,rst.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml b/Documentation/devicetree/bindings/reset/microchip,rst.yaml new file mode 100644 index 000000000000..370579aeeca1 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip Sparx5 Switch Reset Controller + +maintainers: + - Steen Hegelund + - Lars Povlsen + +description: | + The Microchip Sparx5 Switch provides reset control and implements the following + functions + - One Time Switch Core Reset (Soft Reset) + +properties: + $nodename: + pattern: "^reset-controller@[0-9a-f]+$" + + compatible: + const: microchip,sparx5-switch-reset + + reg: + items: + - description: global control block registers + + reg-names: + items: + - const: gcb + + "#reset-cells": + const: 1 + + cpu-syscon: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: syscon used to access CPU reset + +required: + - compatible + - reg + - reg-names + - "#reset-cells" + - cpu-syscon + +additionalProperties: false + +examples: + - | + reset: reset-controller@11010008 { + compatible = "microchip,sparx5-switch-reset"; + reg = <0x11010008 0x4>; + reg-names = "gcb"; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; + }; +