From patchwork Fri Apr 16 13:16:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steen Hegelund X-Patchwork-Id: 12207665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 027C6C433ED for ; Fri, 16 Apr 2021 13:19:52 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 63559611AC for ; Fri, 16 Apr 2021 13:19:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 63559611AC Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=672WLX+NmHA3jyS7TaOrBqNb0e99EM9H4sOYYUVBL0E=; b=Zp8+9Yw9d+byc/3AolosGDiix tV/N7YlTFMKCrO23JRt0+bVZcDBbBvCC6ZO+AurBwyRS4lqOR/fiQ9pjN+UeOX9D7vI/J9aN85jEG /ShID02If0Y7VXlSYguv3Wl9vYs6qZ4+RmA6dN24VlyCHafcy4qMBJH0sNWby3Pu5NaBYSiL7U8pl 5/LxxXS9kA4WcejkyC7fvApSNZWeb0nGjV7B/LJ8Q+NpthRj6mUOpby1f62HWd1qewREhU6tiFoDd KWKLcGKH/QqhQ38uXxvURJTc+8yn0CKVV2ZVhxSLtRLqzl4el2S23DCMe/idZTDn/uwpAPE1grM2f gLhk9sw4w==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lXOLh-002Bb1-Pw; Fri, 16 Apr 2021 13:17:30 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lXOLV-002BZe-PT for linux-arm-kernel@desiato.infradead.org; Fri, 16 Apr 2021 13:17:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Sender:Reply-To:Content-ID:Content-Description; bh=UrlM3PuJOP8ca7SBuGw+IQHz6X48P/ZBBWh9sCeNucY=; b=T2aQtO153PO9OpZMu80P5+VPhs 9T6ofL0jVbITou1ynVYecaN5mhcIQawCZ3aWZkiUYOzvj6pl6fQ0MGrFMzvFhoBTFb0BuWAp1bmFF ZN1mjJrbrz2nAYklYpn65Dv7wInyBraRKseCw9av8rAQgOisIPVKj4mfWovErDhqnaEtysTtgKEcn IvYGXArvmOkTwPPX0hH+S+KlG+WRrS0GPc8CWwNJlucW+arACDrpzNsFHsb8Fc+BVoYHNK1DI4GGn LuiALMSdLmrUHpMdWETSqEwT+TpDdaDM23TPKNA4foLuCIuhVkKj/x1vZ7d4yXCz323pZELyC5iyd 1f8CqHLA==; Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lXOLR-009O2H-QD for linux-arm-kernel@lists.infradead.org; Fri, 16 Apr 2021 13:17:16 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1618579033; x=1650115033; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EDerxEb/j3Egh03qW2BolO+2Li7UvsSGw6FFr4dgaFQ=; b=BcEoTDjQREt98BZRwOZoQ0JK5W7nlJoNRJbc8F76VG+q3PbUdJ6hSoze /1wT+5lrfSzlVkN5DyjU8Vv/obUuviHzpmeXXluSXa8W+h8EsSH5hQ3wc Zfn6pXJ5ym6XDl9mNIeZXrc+U+tL6Olj6xHm/xqRVQGFhibd9YEQ5iLj5 vKeD6/0Le+pvTCGDnpwXxoVkQ8fq0bApwCZyDMawK2g9eakEQr95o2fDW W+XbA+aVbZ8wqGHWd8RqpaMZDtRFFg/LFsbhrnGC3TAXdjon5S+EjhVRg O63yQ3rKWV/vaX7SmxwoZHWPGQ8Ooi7o7F6fDP/dlG1kPkDSToGEZhJ0b g==; IronPort-SDR: +fUFjGKZpcHWTp8eKCyox04M6rmsDMnvmCW4RizBXD7lIMuyMmWbD/DmUx9sVy1Zj9TF+VGs7z CKLIpwoDQRgc2K4/sdi4DlNvoLnQXYrQ/f57bsRAhXsSwVnPcdMe2rXaA7BtTQYWheuUyM4Isw mmTJ0hHs1e/cpT9RG6E04pD2JObSc3w6Ll463Qv0MD12pcUaZ0arlL/iwe/zHbuudmA7prj6IZ 8jqzU2NgvLbzccJK7+NL45p381XyR1Cfk+VuZolqhqzuFrG/7ka2rB9aS7gghGDB5gu3JBNYOK QWg= X-IronPort-AV: E=Sophos;i="5.82,226,1613458800"; d="scan'208";a="111092955" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Apr 2021 06:17:10 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Fri, 16 Apr 2021 06:17:10 -0700 Received: from mchp-dev-shegelun.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Fri, 16 Apr 2021 06:17:06 -0700 From: Steen Hegelund To: "David S. Miller" , Jakub Kicinski , Rob Herring , Device Tree List CC: Steen Hegelund , Andrew Lunn , Russell King , "Microchip Linux Driver Support" , Alexandre Belloni , Madalin Bucur , Mark Einon , Masahiro Yamada , Arnd Bergmann , Philipp Zabel , "Simon Horman" , , , , "Lars Povlsen" , Bjarni Jonasson Subject: [PATCH net-next 01/10] dt-bindings: net: sparx5: Add sparx5-switch bindings Date: Fri, 16 Apr 2021 15:16:48 +0200 Message-ID: <20210416131657.3151464-2-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210416131657.3151464-1-steen.hegelund@microchip.com> References: <20210416131657.3151464-1-steen.hegelund@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210416_061713_937848_E02CF669 X-CRM114-Status: GOOD ( 15.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document the Sparx5 switch device driver bindings Signed-off-by: Steen Hegelund Signed-off-by: Lars Povlsen Signed-off-by: Bjarni Jonasson Reviewed-by: Rob Herring --- .../bindings/net/microchip,sparx5-switch.yaml | 227 ++++++++++++++++++ 1 file changed, 227 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml diff --git a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml new file mode 100644 index 000000000000..2eeb5230d8c8 --- /dev/null +++ b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml @@ -0,0 +1,227 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 Ethernet switch controller + +maintainers: + - Steen Hegelund + - Lars Povlsen + +description: | + The SparX-5 Enterprise Ethernet switch family provides a rich set of + Enterprise switching features such as advanced TCAM-based VLAN and + QoS processing enabling delivery of differentiated services, and + security through TCAM-based frame processing using versatile content + aware processor (VCAP). + + IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported + with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K + IPv6 (S,G) multicast groups. + + L3 security features include source guard and reverse path + forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and + IP tunnels (IP over GRE/IP). + + The SparX-5 switch family targets managed Layer 2 and Layer 3 + equipment in SMB, SME, and Enterprise where high port count + 1G/2.5G/5G/10G switching with 10G/25G aggregation links is required. + +properties: + $nodename: + pattern: "^switch@[0-9a-f]+$" + + compatible: + const: microchip,sparx5-switch + + reg: + minItems: 3 + items: + - description: cpu target + - description: devices target + - description: general control block target + + reg-names: + items: + - const: cpu + - const: devices + - const: gcb + + interrupts: + minItems: 1 + items: + - description: register based extraction + - description: frame dma based extraction + + interrupt-names: + minItems: 1 + items: + - const: xtr + - const: fdma + + resets: + items: + - description: Reset controller used for switch core reset (soft reset) + + reset-names: + items: + - const: switch + + mac-address: true + + ethernet-ports: + type: object + patternProperties: + "^port@[0-9a-f]+$": + type: object + + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + reg: + description: Switch port number + + phys: + maxItems: 1 + description: + phandle of a Ethernet SerDes PHY. This defines which SerDes + instance will handle the Ethernet traffic. + + phy-mode: + description: + This specifies the interface used by the Ethernet SerDes towards + the PHY or SFP. + + microchip,bandwidth: + description: Specifies bandwidth in Mbit/s allocated to the port. + $ref: "/schemas/types.yaml#/definitions/uint32" + maximum: 25000 + + phy-handle: + description: + phandle of a Ethernet PHY. This is optional and if provided it + points to the cuPHY used by the Ethernet SerDes. + + sfp: + description: + phandle of an SFP. This is optional and used when not specifying + a cuPHY. It points to the SFP node that describes the SFP used by + the Ethernet SerDes. + + managed: true + + microchip,sd-sgpio: + description: + Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs + This is optional, and only needed if the default used index is + is not correct. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 383 + + required: + - reg + - phys + - phy-mode + - microchip,bandwidth + + oneOf: + - required: + - phy-handle + - required: + - sfp + - managed + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - resets + - reset-names + - ethernet-ports + +additionalProperties: false + +examples: + - | + #include + switch: switch@600000000 { + compatible = "microchip,sparx5-switch"; + reg = <0 0x401000>, + <0x10004000 0x7fc000>, + <0x11010000 0xaf0000>; + reg-names = "cpu", "devices", "gcb"; + interrupts = ; + interrupt-names = "xtr"; + resets = <&reset 0>; + reset-names = "switch"; + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port0: port@0 { + reg = <0>; + microchip,bandwidth = <1000>; + phys = <&serdes 13>; + phy-handle = <&phy0>; + phy-mode = "qsgmii"; + }; + /* ... */ + /* Then the 25G interfaces */ + port60: port@60 { + reg = <60>; + microchip,bandwidth = <25000>; + phys = <&serdes 29>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth60>; + managed = "in-band-status"; + microchip,sd-sgpio = <365>; + }; + port61: port@61 { + reg = <61>; + microchip,bandwidth = <25000>; + phys = <&serdes 30>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth61>; + managed = "in-band-status"; + microchip,sd-sgpio = <369>; + }; + port62: port@62 { + reg = <62>; + microchip,bandwidth = <25000>; + phys = <&serdes 31>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth62>; + managed = "in-band-status"; + microchip,sd-sgpio = <373>; + }; + port63: port@63 { + reg = <63>; + microchip,bandwidth = <25000>; + phys = <&serdes 32>; + phy-mode = "10gbase-r"; + sfp = <&sfp_eth63>; + managed = "in-band-status"; + microchip,sd-sgpio = <377>; + }; + /* Finally the Management interface */ + port64: port@64 { + reg = <64>; + microchip,bandwidth = <1000>; + phys = <&serdes 0>; + phy-handle = <&phy64>; + phy-mode = "sgmii"; + mac-address = [ 00 00 00 01 02 03 ]; + }; + }; + }; + +... +# vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml :