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bh=BqG+zTglnF7bDNQlesivFzezPjfS1NU3z80UalF/S6Y=; b=fzdt2kczU07HfgMLa/ymOUkja4nB94dtrbmmp3TH6+GS7l4dDtJLkWkItLsPN/MQMP P/PNznJaMZyxIa3HbS+lZIW4V5740QUZVOxZ2QHBh9C/Sghu5rLXE1YPd+M4U3K/sgGN +KElDWnnE+SABeLhxhA6DKQU+KXCz7Fu4+HAkqgk3SSjuNeb4pOcr2W3nh3lgancP2ow QoZaL8aOiS2F+tqrHMLPYOkZQ20v2A5MICz2doIQQOMA8h1KgsFWpzS2pVybjDMfEure +qpQ7Kxpnn4vivFYNheMPXbeyXi4jfeOVRzQ9JUx+FzQgjgqQWoJbFTpHTbvzyrHsQhf pXqQ== X-Gm-Message-State: AOAM531nGKTP1f6Qn5yp4TMNKHiqJ4K6WesJms3BBL9zG/NV6vYAJheB W2zE47KWF+0ZcBvRhUQjN40= X-Google-Smtp-Source: ABdhPJyXEesIOVFoSTI8GDvHdygln2zE5LDKv0dytmwT9xBB8YiKt6cpGaU8lBrUMOCkCPl6DIUf/Q== X-Received: by 2002:a17:902:a585:b029:e7:3d46:660d with SMTP id az5-20020a170902a585b02900e73d46660dmr1326944plb.12.1619064581626; Wed, 21 Apr 2021 21:09:41 -0700 (PDT) Received: from z640-arch.lan ([2602:61:7344:f100::678]) by smtp.gmail.com with ESMTPSA id i17sm635354pfd.84.2021.04.21.21.09.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Apr 2021 21:09:41 -0700 (PDT) From: Ilya Lipnitskiy To: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , "David S. Miller" , Jakub Kicinski , Matthias Brugger , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Cc: Ilya Lipnitskiy Subject: [PATCH net-next 05/14] net: ethernet: mtk_eth_soc: reduce MDIO bus access latency Date: Wed, 21 Apr 2021 21:09:05 -0700 Message-Id: <20210422040914.47788-6-ilya.lipnitskiy@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210422040914.47788-1-ilya.lipnitskiy@gmail.com> References: <20210422040914.47788-1-ilya.lipnitskiy@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210421_210942_409625_DE334C50 X-CRM114-Status: GOOD ( 15.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Felix Fietkau usleep_range often ends up sleeping much longer than the 10-20us provided as a range here. This causes significant latency in mdio bus acceses, which easily adds multiple seconds to the boot time on MT7621 when polling DSA slave ports. Use udelay via readx_poll_timeout_atomic, since the MDIO access does not take much time Signed-off-by: Felix Fietkau [Ilya: use readx_poll_timeout_atomic instead of cond_resched] Signed-off-by: Ilya Lipnitskiy Reviewed-by: Andrew Lunn --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 18 ++++++++---------- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 5cf64de3ddf8..a3958e99a29f 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -79,18 +79,16 @@ static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) static int mtk_mdio_busy_wait(struct mtk_eth *eth) { - unsigned long t_start = jiffies; + int ret; + u32 val; - while (1) { - if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) - return 0; - if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) - break; - usleep_range(10, 20); - } + ret = readx_poll_timeout_atomic(__raw_readl, eth->base + MTK_PHY_IAC, + val, !(val & PHY_IAC_ACCESS), + 5, PHY_IAC_TIMEOUT_US); + if (ret) + dev_err(eth->dev, "mdio: MDIO timeout\n"); - dev_err(eth->dev, "mdio: MDIO timeout\n"); - return -1; + return ret; } static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 875e67b41561..989342a7ae4a 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -327,7 +327,7 @@ #define PHY_IAC_START BIT(16) #define PHY_IAC_ADDR_SHIFT 20 #define PHY_IAC_REG_SHIFT 25 -#define PHY_IAC_TIMEOUT HZ +#define PHY_IAC_TIMEOUT_US 1000000 #define MTK_MAC_MISC 0x1000c #define MTK_MUX_TO_ESW BIT(0)