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bh=+QE5ZWLQU/5/upbp8ywwYoobLbbRgh+EOZbhqiCaUrA=; b=kLjnhWOMVbAwbKH8bY39IEa0ux7c9N56O2RNeQrwlAv9JRHutxfWesJ82HXLGDqCds oHnHTWR7S6F9+YhIhnAnMmn7935MWk541cHqOHQS7w3xM25RE2Y7sEygDm+fhCCjyLOz N2oVqCWtCPbkTTyGGo1e/dbbzoIGBXP/neJhyBNXD/OKL/itAbLm1KZN425jsM6dwchC IC+1D6XggYBH5+02TDm9UkJbyt2Cu+nbGhBCzaJIg2rFq9mFZY9nVu+x8pDwBxh8fQXY t8EWc3vHQxJFow/qlFNFERaDxT0qXDCNZ24EYGg8JN8dy/tePy3I0elFFjTAFsSY4t/v yczw== X-Gm-Message-State: AOAM532mVBFGO4Hw4aG9F77PkRdEuo6aiFknFWPh2Xbe/yD2p+lvIi8u 9rWbC26H+xFZaxtvBn400Cs= X-Google-Smtp-Source: ABdhPJynB6x3ngxSvlU0/QX4s3M24EdwHpWscDh8pUHB5agFFtw8uqjvYdoITIV4mCYf52er8fSdQg== X-Received: by 2002:a63:d755:: with SMTP id w21mr2221158pgi.400.1619155291309; Thu, 22 Apr 2021 22:21:31 -0700 (PDT) Received: from z640-arch.lan ([2602:61:7344:f100::678]) by smtp.gmail.com with ESMTPSA id y24sm6238825pjp.26.2021.04.22.22.21.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 22:21:30 -0700 (PDT) From: Ilya Lipnitskiy To: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , "David S. Miller" , Jakub Kicinski , Matthias Brugger , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Cc: Ilya Lipnitskiy , Andrew Lunn Subject: [PATCH net-next v2 15/15] net: ethernet: mtk_eth_soc: use iopoll.h macro for DMA init Date: Thu, 22 Apr 2021 22:21:08 -0700 Message-Id: <20210423052108.423853-16-ilya.lipnitskiy@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210423052108.423853-1-ilya.lipnitskiy@gmail.com> References: <20210423052108.423853-1-ilya.lipnitskiy@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210423_062347_474748_7A07B6A9 X-CRM114-Status: GOOD ( 15.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Replace a tight busy-wait loop without a pause with a standard readx_poll_timeout_atomic routine with a 5 us poll period. Tested by booting a MT7621 device to ensure the driver initializes properly. Signed-off-by: Ilya Lipnitskiy Reviewed-by: Andrew Lunn --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 29 +++++++++------------ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +- 2 files changed, 14 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 37e50a2e7d0e..ed4eacef17ce 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -2033,25 +2033,22 @@ static int mtk_set_features(struct net_device *dev, netdev_features_t features) /* wait for DMA to finish whatever it is doing before we start using it again */ static int mtk_dma_busy_wait(struct mtk_eth *eth) { - unsigned long t_start = jiffies; + unsigned int reg; + int ret; + u32 val; - while (1) { - if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { - if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & - (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) - return 0; - } else { - if (!(mtk_r32(eth, MTK_PDMA_GLO_CFG) & - (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) - return 0; - } + if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) + reg = MTK_QDMA_GLO_CFG; + else + reg = MTK_PDMA_GLO_CFG; - if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) - break; - } + ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, + !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), + 5, MTK_DMA_BUSY_TIMEOUT_US); + if (ret) + dev_err(eth->dev, "DMA init timeout\n"); - dev_err(eth->dev, "DMA init timeout\n"); - return -1; + return ret; } static int mtk_dma_init(struct mtk_eth *eth) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 6b92dd6c2cda..11331b44ba07 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -214,7 +214,7 @@ #define MTK_TX_DMA_BUSY BIT(1) #define MTK_RX_DMA_EN BIT(2) #define MTK_TX_DMA_EN BIT(0) -#define MTK_DMA_BUSY_TIMEOUT HZ +#define MTK_DMA_BUSY_TIMEOUT_US 1000000 /* QDMA Reset Index Register */ #define MTK_QDMA_RST_IDX 0x1A08