| Message ID | 20210510180601.19458-1-vigneshr@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] arm64: dts: ti: j7200-main: Mark Main NAVSS as dma-coherent | expand |
On Mon, 10 May 2021 23:36:01 +0530, Vignesh Raghavendra wrote: > Traffic through main NAVSS interconnect is coherent wrt ARM caches on > J7200 SoC. Add missing dma-coherent property to main_navss node. > > Also add dma-ranges to be consistent with mcu_navss node > and with AM65/J721e main_navss and mcu_navss nodes. Hi Vignesh Raghavendra, I have applied the following to branch ti-k3-dts-next on [1]. Thank you! [1/1] arm64: dts: ti: j7200-main: Mark Main NAVSS as dma-coherent commit: 52ae30f55a2a40cff549fac95de82f25403bd387 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent up the chain during the next merge window (or sooner if it is a relevant bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. [1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index f86c493a44f1..a6826f1888ef 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -85,6 +85,8 @@ main_navss: bus@30000000 { #size-cells = <2>; ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; ti,sci-dev-id = <199>; + dma-coherent; + dma-ranges; main_navss_intr: interrupt-controller1 { compatible = "ti,sci-intr";
Traffic through main NAVSS interconnect is coherent wrt ARM caches on J7200 SoC. Add missing dma-coherent property to main_navss node. Also add dma-ranges to be consistent with mcu_navss node and with AM65/J721e main_navss and mcu_navss nodes. Fixes: d361ed88455fe ("arm64: dts: ti: Add support for J7200 SoC") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> --- v2: Pick up Reviewed-by and update commit msg as suggested by Peter v1: https://lore.kernel.org/r/20210427175130.29451-1-vigneshr@ti.com arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++ 1 file changed, 2 insertions(+)