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Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lgK9s-009Iej-0t for linux-arm-kernel@lists.infradead.org; Tue, 11 May 2021 04:38:13 +0000 Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lgK9K-0005c4-3A; Tue, 11 May 2021 06:37:38 +0200 Received: from ore by dude.hi.pengutronix.de with local (Exim 4.92) (envelope-from ) id 1lgK9J-0007yQ-6E; Tue, 11 May 2021 06:37:37 +0200 From: Oleksij Rempel To: Shawn Guo , Sascha Hauer , Andrew Lunn , Florian Fainelli , Heiner Kallweit Cc: Oleksij Rempel , kernel@pengutronix.de, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-imx@nxp.com, Fabio Estevam , David Jander , Russell King , Philippe Schenker Subject: [PATCH v3 4/7] ARM i.MX6q: remove clk-out fixup for the Atheros AR8031 and AR8035 PHYs Date: Tue, 11 May 2021 06:37:32 +0200 Message-Id: <20210511043735.30557-5-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210511043735.30557-1-o.rempel@pengutronix.de> References: <20210511043735.30557-1-o.rempel@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210510_213812_081667_D07C021F X-CRM114-Status: GOOD ( 13.80 ) /bin/ln: failed to access 'reaver_cache/texts/20210510_213812_081667_D07C021F': No such file or directory X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210510_213812_081667_D07C021F X-CRM114-Status: GOOD ( 10.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This configuration should be set over device tree. If this patch breaks network functionality on your system, enable the AT803X_PHY driver and set following device tree property in the PHY node: qca,clk-out-frequency = <125000000>; Signed-off-by: Oleksij Rempel Reviewed-by: Andrew Lunn --- arch/arm/mach-imx/mach-imx6q.c | 30 ------------------------------ 1 file changed, 30 deletions(-) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 4c840e116003..d12b571a61ac 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -68,25 +68,6 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup); -static int ar8031_phy_fixup(struct phy_device *dev) -{ - u16 val; - - /* To enable AR8031 output a 125MHz clk from CLK_25M */ - phy_write(dev, 0xd, 0x7); - phy_write(dev, 0xe, 0x8016); - phy_write(dev, 0xd, 0x4007); - - val = phy_read(dev, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(dev, 0xe, val); - - return 0; -} - -#define PHY_ID_AR8031 0x004dd074 - static int ar8035_phy_fixup(struct phy_device *dev) { u16 val; @@ -101,15 +82,6 @@ static int ar8035_phy_fixup(struct phy_device *dev) val = phy_read(dev, 0xe); phy_write(dev, 0xe, val & ~(1 << 8)); - /* - * Enable 125MHz clock from CLK_25M on the AR8031. This - * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad. - * Also, introduce a tx clock delay. - * - * This is the same as is the AR8031 fixup. - */ - ar8031_phy_fixup(dev); - return 0; } @@ -120,8 +92,6 @@ static void __init imx6q_enet_phy_init(void) if (IS_BUILTIN(CONFIG_PHYLIB)) { phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, ksz9021rn_phy_fixup); - phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffef, - ar8031_phy_fixup); phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef, ar8035_phy_fixup); }