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bh=76IdugtbClFxLj74WNNMpYQI/ftacptYSE6W5nWHEcc=; b=JCfTVCXj23F8Q94fVFXDBq9F0oL6k78LJ9aB/m08VcLXd5AVSOFcYy8hq9wjj0xD0v Lcb2mygEyBXtieCwSAbPlMoiLSeN/Z9BalU9I2uL8/S8D4SPiWUhvHhzaHs72nzZmgFN y1SX9sCzJXndcCQ0+ATrFDaTE7mjb9clnzLB8RobjFqjdcdueYJirowoOYCIv2MvxDDh OzkzWamyCuScCOLA4XtYtG+cSoUGx6wtSvkI5jutWFmvaQyHzgRJEysydlBPXSdTuQCw UWrWjcRR8t3KZuGoGAhHjO4iQB31Z5595FmQlYHuPfcIqfI51OX772jHc5paZ1rx6djx PjDA== X-Gm-Message-State: AOAM533LA7+P/zJmqnyF/3Vuii7aHr50JkDAEhbsRWar9vkxXUOnBn6v CvGNJVGeV4EbhNfdB1C2ASQaPQ== X-Google-Smtp-Source: ABdhPJwKnlbJ4gpNyi4xk/Vv42orcu0jI44ghxbD2ytgRG+DksweHVfAME0KE1tF0F2TJKW6puNYEA== X-Received: by 2002:adf:cc92:: with SMTP id p18mr11384097wrj.87.1620854286367; Wed, 12 May 2021 14:18:06 -0700 (PDT) Received: from linaro.org ([2a00:23c5:6809:2201:3d54:dc15:c65b:180c]) by smtp.gmail.com with ESMTPSA id e10sm908745wrw.20.2021.05.12.14.18.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 May 2021 14:18:06 -0700 (PDT) From: Mike Leach To: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org, mathieu.poirier@linaro.org, suzuki.poulose@arm.com, leo.yan@linaro.org, Mike Leach Subject: [RFC PATCH 8/8] coresight: etm4x: Update configuration example. Date: Wed, 12 May 2021 22:17:52 +0100 Message-Id: <20210512211752.4103-9-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210512211752.4103-1-mike.leach@linaro.org> References: <20210512211752.4103-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210512_141807_900279_950DC901 X-CRM114-Status: GOOD ( 12.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Update autofdo configuration and etm4 strobing feature example to use new resource allocation methods. Signed-off-by: Mike Leach --- .../hwtracing/coresight/coresight-cfg-afdo.c | 38 +++++++++---------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cfg-afdo.c b/drivers/hwtracing/coresight/coresight-cfg-afdo.c index 84b31184252b..cae142827d44 100644 --- a/drivers/hwtracing/coresight/coresight-cfg-afdo.c +++ b/drivers/hwtracing/coresight/coresight-cfg-afdo.c @@ -30,63 +30,63 @@ static struct cscfg_regval_desc strobe_regs[] = { /* resource selectors */ { .type = CS_CFG_REG_TYPE_RESOURCE, - .offset = TRCRSCTLRn(2), + .offset = 2, .hw_info = ETM4_CFG_RES_SEL, .val32 = 0x20001, }, { .type = CS_CFG_REG_TYPE_RESOURCE, - .offset = TRCRSCTLRn(3), - .hw_info = ETM4_CFG_RES_SEQ, + .offset = 3, + .hw_info = ETM4_CFG_RES_SEL, .val32 = 0x20002, }, /* strobe window counter 0 - reload from param 0 */ { .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_SAVE, - .offset = TRCCNTVRn(0), - .hw_info = ETM4_CFG_RES_CTR, + .offset = 0, + .hw_info = ETM4_CFG_RES_CTR | ETM4_CTR_VAL, }, { .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_PARAM, - .offset = TRCCNTRLDVRn(0), - .hw_info = ETM4_CFG_RES_CTR, + .offset = 0, + .hw_info = ETM4_CFG_RES_CTR | ETM4_CTR_RLD, .val32 = 0, }, { .type = CS_CFG_REG_TYPE_RESOURCE, - .offset = TRCCNTCTLRn(0), - .hw_info = ETM4_CFG_RES_CTR, + .offset = 0, + .hw_info = ETM4_CFG_RES_CTR | ETM4_CTR_CTRL, .val32 = 0x10001, }, /* strobe period counter 1 - reload from param 1 */ { .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_SAVE, - .offset = TRCCNTVRn(1), - .hw_info = ETM4_CFG_RES_CTR, + .offset = 1, + .hw_info = ETM4_CFG_RES_CTR | ETM4_CTR_VAL, }, { .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_PARAM, - .offset = TRCCNTRLDVRn(1), - .hw_info = ETM4_CFG_RES_CTR, + .offset = 1, + .hw_info = ETM4_CFG_RES_CTR | ETM4_CTR_RLD, .val32 = 1, }, { .type = CS_CFG_REG_TYPE_RESOURCE, - .offset = TRCCNTCTLRn(1), - .hw_info = ETM4_CFG_RES_CTR, + .offset = 1, + .hw_info = ETM4_CFG_RES_CTR | ETM4_CTR_CTRL, .val32 = 0x8102, }, /* sequencer */ { .type = CS_CFG_REG_TYPE_RESOURCE, - .offset = TRCSEQEVRn(0), - .hw_info = ETM4_CFG_RES_SEQ, + .offset = 0, + .hw_info = ETM4_CFG_RES_SEQ | ETM4_SEQ_STATE_R, .val32 = 0x0081, }, { .type = CS_CFG_REG_TYPE_RESOURCE, - .offset = TRCSEQEVRn(1), - .hw_info = ETM4_CFG_RES_SEQ, + .offset = 1, + .hw_info = ETM4_CFG_RES_SEQ | ETM4_SEQ_STATE_R, .val32 = 0x0000, }, /* view-inst */