| Message ID | 20210517171205.1581938-3-abelvesa@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: freescale: Add i.MX8DXL support | expand |
On Tue, May 18, 2021 at 1:14 AM <abelvesa@kernel.org> wrote: > > From: Abel Vesa <abel.vesa@nxp.com> > > The mailbox of the lsio mu5a is used by rpmsg on imx8qxp and > imx8dxl platforms. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi > index ee4e585a9c39..8e3c92c82fac 100644 > --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi > @@ -141,6 +141,15 @@ lsio_mu4: mailbox@5d1f0000 { > status = "disabled"; > }; > > + lsio_mu5: mailbox@5d200000 { > + compatible = "fsl,imx6sx-mu"; For normal devices node, the compatible string are prefered to be defined in soc-ss-xxx.dtsi in case to handle HW minus difference. e.g. mu13 > + reg = <0x5d200000 0x10000>; > + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; > + #mbox-cells = <2>; > + power-domains = <&pd IMX_SC_R_MU_5A>; > + }; > + > + > lsio_mu13: mailbox@5d280000 { > reg = <0x5d280000 0x10000>; > interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; > -- > 2.31.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On 21-05-18 15:50:51, Dong Aisheng wrote: > On Tue, May 18, 2021 at 1:14 AM <abelvesa@kernel.org> wrote: > > > > From: Abel Vesa <abel.vesa@nxp.com> > > > > The mailbox of the lsio mu5a is used by rpmsg on imx8qxp and > > imx8dxl platforms. > > > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 9 +++++++++ > > 1 file changed, 9 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi > > index ee4e585a9c39..8e3c92c82fac 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi > > @@ -141,6 +141,15 @@ lsio_mu4: mailbox@5d1f0000 { > > status = "disabled"; > > }; > > > > + lsio_mu5: mailbox@5d200000 { > > + compatible = "fsl,imx6sx-mu"; > > For normal devices node, the compatible string are prefered to be > defined in soc-ss-xxx.dtsi > in case to handle HW minus difference. e.g. mu13 > Moved it to imx8dxl-ss-lsio.dtsi. > > > + reg = <0x5d200000 0x10000>; > > + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; > > + #mbox-cells = <2>; > > + power-domains = <&pd IMX_SC_R_MU_5A>; > > + }; > > + > > + > > lsio_mu13: mailbox@5d280000 { > > reg = <0x5d280000 0x10000>; > > interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; > > -- > > 2.31.1 > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@lists.infradead.org > > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&data=04%7C01%7Cabel.vesa%40nxp.com%7C868b5c19cea64f7f3e4008d919d1ce23%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637569211161280172%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=z2cyzPRkkbHM8LgNIW97x5iPn%2BOjHlqSUvAaJ6%2BAOck%3D&reserved=0
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index ee4e585a9c39..8e3c92c82fac 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -141,6 +141,15 @@ lsio_mu4: mailbox@5d1f0000 { status = "disabled"; }; + lsio_mu5: mailbox@5d200000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x5d200000 0x10000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_5A>; + }; + + lsio_mu13: mailbox@5d280000 { reg = <0x5d280000 0x10000>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;