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bh=UMV7QsTgPPQWeHZACgAJTLak2uBSFbgGNVbitXpkumY=; b=bntASmcLswCFwpWvvfjEcj06dZ+nWxc51OUqOplrCZLxnH7rAOY++xFL7qlzF4Y/hB PTSlvxNlZ4xRl6t2Bswjn8T7NLyFbM6Fb1hSmcxhCbaozPG+PzenzcfM2+b4qAgYHSnG 7shEvIDEM18n+eS7r/jUK9f4PLVZv/3INUSBYWjd9gnrRC88mGJhHCeT8gdGrhZns0tx W5p9ig2vWE3RdT/HnAcOxrVO2Wmzum06slaAM6YyQv80ouKBuKo33dntiGsczA8IETZr i8+m61i70qU6cNNekIvDpAHT48dm6O9BSrSAfVd3p1uQtJCClbun8H+Ixxebi1HMoupV +5EA== X-Gm-Message-State: AOAM531p2Y9KCGsdo9hJzCqxZMd9hABxQ2D9P6uMkyA0swE95B/B+XOA MiLeuq7/UJI/Iwe56b8qLVg= X-Google-Smtp-Source: ABdhPJzIFT/6iKFcpgqqZGn/WXeltIuFnyxwyWHx+EoZfc1DaoTOk8qlYPNqJ1+vWpugaseUlQyLRA== X-Received: by 2002:a05:620a:4543:: with SMTP id u3mr549497qkp.118.1621446116804; Wed, 19 May 2021 10:41:56 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:de7c:b0e3:ef92:cf37]) by smtp.gmail.com with ESMTPSA id k125sm280021qkf.53.2021.05.19.10.41.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 May 2021 10:41:56 -0700 (PDT) From: Peter Geis To: Michael Turquette , Stephen Boyd , Heiko Stuebner , Kever Yang , Elaine Zhang Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Geis Subject: [PATCH] clk: rockchip: fix rk3568 cpll clk gate bits Date: Wed, 19 May 2021 13:41:49 -0400 Message-Id: <20210519174149.3691335-1-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210519_104158_963319_3D412BF0 X-CRM114-Status: GOOD ( 12.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The cpll clk gate bits had an ordering issue. This led to the loss of the boot sdmmc controller when the gmac was shut down with: `ip link set eth0 down` as the cpll_100m was shut off instead of the cpll_62p5. cpll_62p5, cpll_50m, cpll_25m were all off by one with cpll_100m misplaced. Fixes: cf911d89c4c5 ("clk: rockchip: add clock controller for rk3568") Signed-off-by: Peter Geis Reviewed-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3568.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 946ea2f45bf3..75ca855e720d 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -454,17 +454,17 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(80), 0, 5, DFLAGS, RK3568_CLKGATE_CON(35), 10, GFLAGS), + COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(82), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 11, GFLAGS), COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(80), 8, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 11, GFLAGS), + RK3568_CLKGATE_CON(35), 12, GFLAGS), COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(81), 0, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 12, GFLAGS), + RK3568_CLKGATE_CON(35), 13, GFLAGS), COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(81), 8, 6, DFLAGS, - RK3568_CLKGATE_CON(35), 13, GFLAGS), - COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(82), 0, 5, DFLAGS, RK3568_CLKGATE_CON(35), 14, GFLAGS), COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(82), 8, 6, DFLAGS,