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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=oss.nxp.com; Received: from DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) by DBBPR04MB7515.eurprd04.prod.outlook.com (2603:10a6:10:202::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.24; Fri, 28 May 2021 11:01:12 +0000 Received: from DB6PR0402MB2760.eurprd04.prod.outlook.com ([fe80::45b9:c993:87ec:9a64]) by DB6PR0402MB2760.eurprd04.prod.outlook.com ([fe80::45b9:c993:87ec:9a64%8]) with mapi id 15.20.4173.024; Fri, 28 May 2021 11:01:12 +0000 From: "Peng Fan (OSS)" To: sboyd@kernel.org, mturquette@baylibre.com Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, Peng Fan Subject: [PATCH 1/3] clk: mux: support regmap Date: Fri, 28 May 2021 19:34:01 +0800 Message-Id: <20210528113403.5374-2-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210528113403.5374-1-peng.fan@oss.nxp.com> References: <20210528113403.5374-1-peng.fan@oss.nxp.com> X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: SG2PR06CA0158.apcprd06.prod.outlook.com (2603:1096:1:1e::12) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR06CA0158.apcprd06.prod.outlook.com (2603:1096:1:1e::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.20 via Frontend Transport; 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So let's use regmap here. Signed-off-by: Peng Fan --- drivers/clk/clk-mux.c | 26 +++++++++++++++++++++++--- include/linux/clk-provider.h | 6 ++++++ 2 files changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 20582aae7a35..90facb6eafe6 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -26,18 +27,37 @@ static inline u32 clk_mux_readl(struct clk_mux *mux) { - if (mux->flags & CLK_MUX_BIG_ENDIAN) + int ret; + uint32_t val; + + if (mux->flags & CLK_MUX_BIG_ENDIAN) { return ioread32be(mux->reg); + } else if (mux->flags & CLK_MUX_REGMAP) { + ret = regmap_read(mux->regmap, mux->reg_off, &val); + if (ret < 0) { + pr_warn("%s: failed read %x, %d\n", __func__, mux->reg_off, ret); + return ret; + } else { + return val; + } + } return readl(mux->reg); } static inline void clk_mux_writel(struct clk_mux *mux, u32 val) { - if (mux->flags & CLK_MUX_BIG_ENDIAN) + int ret; + + if (mux->flags & CLK_MUX_BIG_ENDIAN) { iowrite32be(val, mux->reg); - else + } else if (mux->flags & CLK_MUX_REGMAP) { + ret = regmap_write(mux->regmap, mux->reg_off, val); + if (ret < 0) + pr_warn("%s: failed write %x, %d\n", __func__, mux->reg_off, ret); + } else { writel(val, mux->reg); + } } int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 162a2e5546a3..6bd9288b953d 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -837,6 +837,8 @@ void clk_hw_unregister_divider(struct clk_hw *hw); * @mask: mask of mutliplexer bit field * @flags: hardware-specific flags * @lock: register lock + * @regmap: register controlling regmap + * @reg_off: register offset * * Clock with multiple selectable parents. Implements .get_parent, .set_parent * and .recalc_rate @@ -855,6 +857,7 @@ void clk_hw_unregister_divider(struct clk_hw *hw); * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for * the mux register. Setting this flag makes the register accesses big * endian. + * CLK_MUX_REGMAP - Indicate the accessing method is using regmap API. */ struct clk_mux { struct clk_hw hw; @@ -864,6 +867,8 @@ struct clk_mux { u8 shift; u8 flags; spinlock_t *lock; + struct regmap *regmap; + u32 reg_off; }; #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) @@ -874,6 +879,7 @@ struct clk_mux { #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ #define CLK_MUX_ROUND_CLOSEST BIT(4) #define CLK_MUX_BIG_ENDIAN BIT(5) +#define CLK_MUX_REGMAP BIT(6) extern const struct clk_ops clk_mux_ops; extern const struct clk_ops clk_mux_ro_ops;