diff mbox series

[v2] dt-bindings: rtc: zynqmp: convert bindings to YAML

Message ID 20210602000918.779983-1-iwamatsu@nigauri.org (mailing list archive)
State New, archived
Headers show
Series [v2] dt-bindings: rtc: zynqmp: convert bindings to YAML | expand

Commit Message

Nobuhiro Iwamatsu June 2, 2021, 12:09 a.m. UTC
Convert Real Time Clock for Xilinx Zynq MPSoC SoC bindings documentation
to YAML schemas.
And this renamed the file to compatible string of DT.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---

v2: Fix warning with DT_CHECKER_FLAGS=-m

 .../bindings/rtc/xlnx,zynqmp-rtc.yaml         | 61 +++++++++++++++++++
 .../devicetree/bindings/rtc/xlnx-rtc.txt      | 25 --------
 2 files changed, 61 insertions(+), 25 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
 delete mode 100644 Documentation/devicetree/bindings/rtc/xlnx-rtc.txt

Comments

Rob Herring (Arm) June 10, 2021, 5:21 p.m. UTC | #1
On Wed, Jun 02, 2021 at 09:09:18AM +0900, Nobuhiro Iwamatsu wrote:
> Convert Real Time Clock for Xilinx Zynq MPSoC SoC bindings documentation
> to YAML schemas.
> And this renamed the file to compatible string of DT.
> 
> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
> ---
> 
> v2: Fix warning with DT_CHECKER_FLAGS=-m
> 
>  .../bindings/rtc/xlnx,zynqmp-rtc.yaml         | 61 +++++++++++++++++++
>  .../devicetree/bindings/rtc/xlnx-rtc.txt      | 25 --------
>  2 files changed, 61 insertions(+), 25 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
>  delete mode 100644 Documentation/devicetree/bindings/rtc/xlnx-rtc.txt
> 
> diff --git a/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
> new file mode 100644
> index 00000000000000..c205cb86ef00be
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
> +
> +description: |

Don't need '|'

> +  RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
> +  This separates IRQ lines for seconds and alarm.

The RTC controller has separate IRQ...

> +
> +maintainers:
> +  - Michal Simek <michal.simek@xilinx.com>
> +
> +allOf:
> +  - $ref: rtc.yaml#
> +
> +properties:
> +  compatible:
> +    const: xlnx,zynqmp-rtc
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    minItems: 2
> +
> +  interrupt-names:
> +    items:
> +      - const: alarm
> +      - const: sec
> +
> +  calibration:
> +    description: |
> +      calibration value for 1 sec period which will
> +      be programmed directly to calibration register.

Needs a type $ref.

> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - interrupt-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    soc {
> +      #address-cells = <2>;
> +      #size-cells = <2>;
> +
> +      rtc: rtc@ffa60000 {
> +        compatible = "xlnx,zynqmp-rtc";
> +        reg = <0x0 0xffa60000 0x0 0x100>;
> +        interrupt-parent = <&gic>;
> +        interrupts = <0 26 4>, <0 27 4>;
> +        interrupt-names = "alarm", "sec";
> +        calibration = <0x198233>;
> +      };
> +    };
Nobuhiro Iwamatsu June 11, 2021, 10:07 p.m. UTC | #2
Hi,

Thanks for your review.

2021年6月11日(金) 2:21 Rob Herring <robh@kernel.org>:
>
> On Wed, Jun 02, 2021 at 09:09:18AM +0900, Nobuhiro Iwamatsu wrote:
> > Convert Real Time Clock for Xilinx Zynq MPSoC SoC bindings documentation
> > to YAML schemas.
> > And this renamed the file to compatible string of DT.
> >
> > Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
> > ---
> >
> > v2: Fix warning with DT_CHECKER_FLAGS=-m
> >
> >  .../bindings/rtc/xlnx,zynqmp-rtc.yaml         | 61 +++++++++++++++++++
> >  .../devicetree/bindings/rtc/xlnx-rtc.txt      | 25 --------
> >  2 files changed, 61 insertions(+), 25 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
> >  delete mode 100644 Documentation/devicetree/bindings/rtc/xlnx-rtc.txt
> >
> > diff --git a/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
> > new file mode 100644
> > index 00000000000000..c205cb86ef00be
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
> > @@ -0,0 +1,61 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
> > +
> > +description: |
>
> Don't need '|'

OK, I will drop.

>
> > +  RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
> > +  This separates IRQ lines for seconds and alarm.
>
> The RTC controller has separate IRQ...

I will update description, thanks.

>
> > +
> > +maintainers:
> > +  - Michal Simek <michal.simek@xilinx.com>
> > +
> > +allOf:
> > +  - $ref: rtc.yaml#
> > +
> > +properties:
> > +  compatible:
> > +    const: xlnx,zynqmp-rtc
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    minItems: 2
> > +
> > +  interrupt-names:
> > +    items:
> > +      - const: alarm
> > +      - const: sec
> > +
> > +  calibration:
> > +    description: |
> > +      calibration value for 1 sec period which will
> > +      be programmed directly to calibration register.
>
> Needs a type $ref.

OK, I will add $ref.

>
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - interrupt-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    soc {
> > +      #address-cells = <2>;
> > +      #size-cells = <2>;
> > +
> > +      rtc: rtc@ffa60000 {
> > +        compatible = "xlnx,zynqmp-rtc";
> > +        reg = <0x0 0xffa60000 0x0 0x100>;
> > +        interrupt-parent = <&gic>;
> > +        interrupts = <0 26 4>, <0 27 4>;
> > +        interrupt-names = "alarm", "sec";
> > +        calibration = <0x198233>;
> > +      };
> > +    };

Best regards,
  Nobuhiro
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
new file mode 100644
index 00000000000000..c205cb86ef00be
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
@@ -0,0 +1,61 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
+
+description: |
+  RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
+  This separates IRQ lines for seconds and alarm.
+
+maintainers:
+  - Michal Simek <michal.simek@xilinx.com>
+
+allOf:
+  - $ref: rtc.yaml#
+
+properties:
+  compatible:
+    const: xlnx,zynqmp-rtc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    minItems: 2
+
+  interrupt-names:
+    items:
+      - const: alarm
+      - const: sec
+
+  calibration:
+    description: |
+      calibration value for 1 sec period which will
+      be programmed directly to calibration register.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      rtc: rtc@ffa60000 {
+        compatible = "xlnx,zynqmp-rtc";
+        reg = <0x0 0xffa60000 0x0 0x100>;
+        interrupt-parent = <&gic>;
+        interrupts = <0 26 4>, <0 27 4>;
+        interrupt-names = "alarm", "sec";
+        calibration = <0x198233>;
+      };
+    };
diff --git a/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt b/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt
deleted file mode 100644
index 0df6f016b1b771..00000000000000
--- a/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt
+++ /dev/null
@@ -1,25 +0,0 @@ 
-* Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
-
-RTC controller for the Xilinx Zynq MPSoC Real Time Clock
-Separate IRQ lines for seconds and alarm
-
-Required properties:
-- compatible: Should be "xlnx,zynqmp-rtc"
-- reg: Physical base address of the controller and length
-       of memory mapped region.
-- interrupts: IRQ lines for the RTC.
-- interrupt-names: interrupt line names eg. "sec" "alarm"
-
-Optional:
-- calibration: calibration value for 1 sec period which will
-		be programmed directly to calibration register
-
-Example:
-rtc: rtc@ffa60000 {
-	compatible = "xlnx,zynqmp-rtc";
-	reg = <0x0 0xffa60000 0x100>;
-	interrupt-parent = <&gic>;
-	interrupts = <0 26 4>, <0 27 4>;
-	interrupt-names = "alarm", "sec";
-	calibration = <0x198233>;
-};