| Message ID | 20210604090943.3519350-3-aisheng.dong@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: imx: scu: add more scu clock features | expand |
On 21-06-04 17:09:35, Dong Aisheng wrote: > From: "Guoniu.zhou" <guoniu.zhou@nxp.com> > > Because digital pll for parallel interface is on by default, and > not provide enable/disable function by scu, so add the related ops > for this kind of clocks. > > Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> This looks OK to me. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> > --- > drivers/clk/imx/clk-scu.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c > index f4efb3b76c86..680b2650fd45 100644 > --- a/drivers/clk/imx/clk-scu.c > +++ b/drivers/clk/imx/clk-scu.c > @@ -425,6 +425,12 @@ static const struct clk_ops clk_scu_cpu_ops = { > .unprepare = clk_scu_unprepare, > }; > > +static const struct clk_ops clk_scu_pi_ops = { > + .recalc_rate = clk_scu_recalc_rate, > + .round_rate = clk_scu_round_rate, > + .set_rate = clk_scu_set_rate, > +}; > + > struct clk_hw *__imx_clk_scu(struct device *dev, const char *name, > const char * const *parents, int num_parents, > u32 rsrc_id, u8 clk_type) > @@ -445,6 +451,8 @@ struct clk_hw *__imx_clk_scu(struct device *dev, const char *name, > init.ops = &clk_scu_ops; > if (rsrc_id == IMX_SC_R_A35) > init.ops = &clk_scu_cpu_ops; > + else if (rsrc_id == IMX_SC_R_PI_0_PLL) > + init.ops = &clk_scu_pi_ops; > else > init.ops = &clk_scu_ops; > init.parent_names = parents; > -- > 2.25.1 >
diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index f4efb3b76c86..680b2650fd45 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -425,6 +425,12 @@ static const struct clk_ops clk_scu_cpu_ops = { .unprepare = clk_scu_unprepare, }; +static const struct clk_ops clk_scu_pi_ops = { + .recalc_rate = clk_scu_recalc_rate, + .round_rate = clk_scu_round_rate, + .set_rate = clk_scu_set_rate, +}; + struct clk_hw *__imx_clk_scu(struct device *dev, const char *name, const char * const *parents, int num_parents, u32 rsrc_id, u8 clk_type) @@ -445,6 +451,8 @@ struct clk_hw *__imx_clk_scu(struct device *dev, const char *name, init.ops = &clk_scu_ops; if (rsrc_id == IMX_SC_R_A35) init.ops = &clk_scu_cpu_ops; + else if (rsrc_id == IMX_SC_R_PI_0_PLL) + init.ops = &clk_scu_pi_ops; else init.ops = &clk_scu_ops; init.parent_names = parents;