@@ -694,6 +694,90 @@ mailbox0_cluster7: mailbox@29070000 {
ti,mbox-num-fifos = <16>;
};
+ main_r5fss0: r5fss@78000000 {
+ compatible = "ti,am64-r5fss";
+ ti,cluster-mode = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x78000000 0x00 0x78000000 0x10000>,
+ <0x78100000 0x00 0x78100000 0x10000>,
+ <0x78200000 0x00 0x78200000 0x08000>,
+ <0x78300000 0x00 0x78300000 0x08000>;
+ power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss0_core0: r5f@78000000 {
+ compatible = "ti,am64-r5f";
+ reg = <0x78000000 0x00010000>,
+ <0x78100000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <121>;
+ ti,sci-proc-ids = <0x01 0xff>;
+ resets = <&k3_reset 121 1>;
+ firmware-name = "am64-main-r5f0_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ main_r5fss0_core1: r5f@78200000 {
+ compatible = "ti,am64-r5f";
+ reg = <0x78200000 0x00008000>,
+ <0x78300000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <122>;
+ ti,sci-proc-ids = <0x02 0xff>;
+ resets = <&k3_reset 122 1>;
+ firmware-name = "am64-main-r5f0_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+
+ main_r5fss1: r5fss@78400000 {
+ compatible = "ti,am64-r5fss";
+ ti,cluster-mode = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x78400000 0x00 0x78400000 0x10000>,
+ <0x78500000 0x00 0x78500000 0x10000>,
+ <0x78600000 0x00 0x78600000 0x08000>,
+ <0x78700000 0x00 0x78700000 0x08000>;
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss1_core0: r5f@78400000 {
+ compatible = "ti,am64-r5f";
+ reg = <0x78400000 0x00010000>,
+ <0x78500000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <123>;
+ ti,sci-proc-ids = <0x06 0xff>;
+ resets = <&k3_reset 123 1>;
+ firmware-name = "am64-main-r5f1_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ main_r5fss1_core1: r5f@78600000 {
+ compatible = "ti,am64-r5f";
+ reg = <0x78600000 0x00008000>,
+ <0x78700000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <124>;
+ ti,sci-proc-ids = <0x07 0xff>;
+ resets = <&k3_reset 124 1>;
+ firmware-name = "am64-main-r5f1_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+
serdes_wiz0: wiz@f000000 {
compatible = "ti,am64-wiz-10g";
#address-cells = <1>;
The AM64x SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. Both the R5F clusters are present within the MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be configured at boot time to be either run in a new "Single-CPU" mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. The mode is restricted to "Single-CPU" on some devices with the appropriate eFuse bit set, but the most common devices support both modes. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). The TCMs of both Cores are combined in Single-CPU mode to provide a larger 128 KB of memory. The other notable difference is that the TCMs are spaced 1 MB apart on these SoCs unlike the existing SoCs. Add the DT nodes for both these MAIN domain R5F cluster/subsystems, the two R5F cores are added as child nodes to each of the corresponding R5F cluster node. Both the clusters are configured to run in Split mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if desired: MAIN R5FSS0 Core0: am64-main-r5f0_0-fw (both in Single-CPU & Split modes) MAIN R5FSS0 Core1: am64-main-r5f0_1-fw (needed only in Split mode) MAIN R5FSS1 Core0: am64-main-r5f1_0-fw (both in Single-CPU & Split modes) MAIN R5FSS1 Core1: am64-main-r5f1_1-fw (needed only in Split mode) NOTE: A R5FSS cluster can be configured in "Single-CPU" mode by using a value of 2 for the "ti,cluster-mode" property. Value of 1 is not permitted (fails the dtbs_check). Signed-off-by: Suman Anna <s-anna@ti.com> --- v2: No code changes, rebased and retained the presence after the mailbox nodes arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 84 ++++++++++++++++++++++++ 1 file changed, 84 insertions(+)