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Mon, 21 Jun 2021 00:25:33 -0700 (PDT) From: Jagan Teki To: Peng Fan , Shawn Guo , Sascha Hauer , Tomasz Figa , Fancy Fang Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, NXP Linux Team , linux-amarula@amarulasolutions.com, Anthony Brandon , Francis Laniel , Matteo Lisi , Milco Pratesi , Jagan Teki , Rob Herring Subject: [RFC PATCH 8/9] arm64: dts: imx8mm: Add MIPI DSI pipeline Date: Mon, 21 Jun 2021 12:54:23 +0530 Message-Id: <20210621072424.111733-9-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210621072424.111733-1-jagan@amarulasolutions.com> References: <20210621072424.111733-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210621_002534_522863_4D6196E9 X-CRM114-Status: GOOD ( 11.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add MIPI DSI pipeline for i.MX8MM. Video pipeline start from eLCDIF to MIPI DSI and respective Panel or Bridge on the backend side. Add support for it. Cc: Rob Herring Signed-off-by: Jagan Teki --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 59 +++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 5f68182ed3a6..bc09fce0f6a9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1047,6 +1047,65 @@ lcdif: lcdif@32e00000 { interrupts = ; power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_LCDIF>; status = "disabled"; + + port { + lcdif_out_dsi: endpoint { + remote-endpoint = <&dsi_in_lcdif>; + }; + }; + }; + + dsi: dsi@32e10000 { + compatible = "fsl,imx8mm-sec-dsim"; + reg = <0x32e10000 0xa0>; + clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + clock-names = "bus", "phy_ref"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_VIDEO_PLL1_BYPASS>, + <&clk IMX8MM_VIDEO_PLL1_OUT>; + assigned-clock-rates = <266000000>, <594000000>, <27000000>; + interrupts = ; + phys = <&dphy>; + phy-names = "dphy"; + power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DSI>; + samsung,burst-clock-frequency = <891000000>; + samsung,esc-clock-frequency = <54000000>; + samsung,pll-clock-frequency = <27000000>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi_in_lcdif: endpoint@0 { + reg = <0>; + remote-endpoint = <&lcdif_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + dphy: dphy@32e100a4 { + compatible = "fsl,imx8mm-sec-dsim-dphy"; + reg = <0x32e100a4 0xbc>; + clocks = <&clk IMX8MM_CLK_DSI_PHY_REF>; + clock-names = "phy_ref"; + #phy-cells = <0>; + power-domains = <&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DPHY>; + status = "disabled"; }; dispmix_blk_ctl: blk-ctl@32e28000 {