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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=L+cprSIOQwMBhX/Dcpl4mCFeR5CoPf5e5YRTFC1eYcE=; b=nA3sX416jo+PVBURbeGV3ex3Y6WJzZdORJBIIRMs2Z8JP8i+um4G1MVlqWf/n9+oki fCas2ATN4WDisoZ1dR/Aem1mxL6AWOu5ZTm51YQPzZTUJpFG9tENarqo8NtN3cyCXusZ s3/dS+sY6DwLVMiJtz1j7oKBNwWw6gyjPoHm/Ki+aBOJyX/L/816tfOvVWLt+gKGoFdW litchugMahMOdURZu0m398nHrInGl8xtm9mXeCESVUArMWDqcuxSYQlO7vH6yud1HiFS WkoLJORC387/5g2wYeiOqTcmFfBvCO+Sm826nQfuflZKDbUAKDtwK3OGaKOkOD0BCX6q 9jag== X-Gm-Message-State: AOAM533dMziYWHeZ7tAkEE0+7ydg8/PEFXSHufW1aU/9pLTp07uEHyvn mcHNNnefVqhJ+JslmNFjjN1ZzmA= X-Google-Smtp-Source: ABdhPJwdoheS1UHLrTgG4pnRKYMYpOoOAZ0CGfvEIyxlXWSpQVgFYN3RmfxSBOwhhNIwFTRNO00x2YU= X-Received: from pcc-desktop.svl.corp.google.com ([2620:15c:2ce:200:8b00:104d:c249:d343]) (user=pcc job=sendgmr) by 2002:a05:6214:1028:: with SMTP id k8mr40103429qvr.13.1625094920440; Wed, 30 Jun 2021 16:15:20 -0700 (PDT) Date: Wed, 30 Jun 2021 16:15:06 -0700 In-Reply-To: <20210630231509.3773172-1-pcc@google.com> Message-Id: <20210630231509.3773172-2-pcc@google.com> Mime-Version: 1.0 References: <20210630231509.3773172-1-pcc@google.com> X-Mailer: git-send-email 2.32.0.93.g670b81a890-goog Subject: [PATCH v8 1/4] arm64: mte: rename gcr_user_excl to mte_ctrl From: Peter Collingbourne To: Catalin Marinas , Vincenzo Frascino , Will Deacon Cc: Peter Collingbourne , Evgenii Stepanov , Szabolcs Nagy , Tejas Belagod , linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210630_161522_363520_1BF8D48E X-CRM114-Status: GOOD ( 15.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org We are going to use this field to store more data. To prepare for that, rename it and change the users to rely on the bit position of gcr_user_excl in mte_ctrl. Link: https://linux-review.googlesource.com/id/Ie1fd18e480100655f5d22137f5b22f4f3a9f9e2e Signed-off-by: Peter Collingbourne Reviewed-by: Catalin Marinas --- arch/arm64/include/asm/processor.h | 5 ++++- arch/arm64/kernel/asm-offsets.c | 2 +- arch/arm64/kernel/entry.S | 4 ++-- arch/arm64/kernel/mte.c | 14 ++++++++------ 4 files changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index 9df3feeee890..6322fb1714d5 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -16,6 +16,9 @@ */ #define NET_IP_ALIGN 0 +#define MTE_CTRL_GCR_USER_EXCL_SHIFT 0 +#define MTE_CTRL_GCR_USER_EXCL_MASK 0xffff + #ifndef __ASSEMBLY__ #include @@ -151,7 +154,7 @@ struct thread_struct { struct ptrauth_keys_kernel keys_kernel; #endif #ifdef CONFIG_ARM64_MTE - u64 gcr_user_excl; + u64 mte_ctrl; #endif u64 sctlr_user; }; diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c index 0cb34ccb6e73..63d02cd67b44 100644 --- a/arch/arm64/kernel/asm-offsets.c +++ b/arch/arm64/kernel/asm-offsets.c @@ -49,7 +49,7 @@ int main(void) DEFINE(THREAD_KEYS_KERNEL, offsetof(struct task_struct, thread.keys_kernel)); #endif #ifdef CONFIG_ARM64_MTE - DEFINE(THREAD_GCR_EL1_USER, offsetof(struct task_struct, thread.gcr_user_excl)); + DEFINE(THREAD_MTE_CTRL, offsetof(struct task_struct, thread.mte_ctrl)); #endif BLANK(); DEFINE(S_X0, offsetof(struct pt_regs, regs[0])); diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 3513984a88bd..ce59280355c5 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -182,7 +182,7 @@ alternative_else_nop_endif * the RRND (bit[16]) setting. */ mrs_s \tmp2, SYS_GCR_EL1 - bfi \tmp2, \tmp, #0, #16 + bfxil \tmp2, \tmp, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16 msr_s SYS_GCR_EL1, \tmp2 #endif .endm @@ -205,7 +205,7 @@ alternative_else_nop_endif alternative_if_not ARM64_MTE b 1f alternative_else_nop_endif - ldr \tmp, [\tsk, #THREAD_GCR_EL1_USER] + ldr \tmp, [\tsk, #THREAD_MTE_CTRL] mte_set_gcr \tmp, \tmp2 1: diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c index 125a10e413e9..d3884d09513d 100644 --- a/arch/arm64/kernel/mte.c +++ b/arch/arm64/kernel/mte.c @@ -199,7 +199,7 @@ static void update_gcr_el1_excl(u64 excl) static void set_gcr_el1_excl(u64 excl) { - current->thread.gcr_user_excl = excl; + current->thread.mte_ctrl = excl; /* * SYS_GCR_EL1 will be set to current->thread.gcr_user_excl value @@ -263,8 +263,8 @@ void mte_suspend_exit(void) long set_mte_ctrl(struct task_struct *task, unsigned long arg) { u64 sctlr = task->thread.sctlr_user & ~SCTLR_EL1_TCF0_MASK; - u64 gcr_excl = ~((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT) & - SYS_GCR_EL1_EXCL_MASK; + u64 mte_ctrl = (~((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT) & + SYS_GCR_EL1_EXCL_MASK) << MTE_CTRL_GCR_USER_EXCL_SHIFT; if (!system_supports_mte()) return 0; @@ -285,10 +285,10 @@ long set_mte_ctrl(struct task_struct *task, unsigned long arg) if (task != current) { task->thread.sctlr_user = sctlr; - task->thread.gcr_user_excl = gcr_excl; + task->thread.mte_ctrl = mte_ctrl; } else { set_task_sctlr_el1(sctlr); - set_gcr_el1_excl(gcr_excl); + set_gcr_el1_excl(mte_ctrl); } return 0; @@ -297,7 +297,9 @@ long set_mte_ctrl(struct task_struct *task, unsigned long arg) long get_mte_ctrl(struct task_struct *task) { unsigned long ret; - u64 incl = ~task->thread.gcr_user_excl & SYS_GCR_EL1_EXCL_MASK; + u64 mte_ctrl = task->thread.mte_ctrl; + u64 incl = (~mte_ctrl >> MTE_CTRL_GCR_USER_EXCL_SHIFT) & + SYS_GCR_EL1_EXCL_MASK; if (!system_supports_mte()) return 0;