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[2a01:c23:c041:6f00:f22f:74ff:fe21:725]) by smtp.googlemail.com with ESMTPSA id o11sm3857390wmc.2.2021.07.13.16.25.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 16:25:21 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, jbrunet@baylibre.com, narmstrong@baylibre.com, Martin Blumenstingl Subject: [PATCH 6/6] clk: meson: meson8b: Export the video clocks Date: Wed, 14 Jul 2021 01:25:10 +0200 Message-Id: <20210713232510.3057750-7-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210713232510.3057750-1-martin.blumenstingl@googlemail.com> References: <20210713232510.3057750-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210713_162523_365300_A2215617 X-CRM114-Status: GOOD ( 11.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Setting the video clocks requires fine-tuned adjustments of various video clocks. Export the required ones to allow changing the video clock for the CVBS and HDMI outputs at runtime. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.h | 12 +----------- include/dt-bindings/clock/meson8b-clkc.h | 10 ++++++++++ 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index b5b591943e80..ce62ed47cbfc 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -117,14 +117,11 @@ #define CLKID_PERIPH_SEL 125 #define CLKID_AXI_SEL 127 #define CLKID_L2_DRAM_SEL 129 -#define CLKID_HDMI_PLL_LVDS_OUT 131 -#define CLKID_HDMI_PLL_HDMI_OUT 132 +#define CLKID_HDMI_PLL_LVDS_OUT 131 #define CLKID_VID_PLL_IN_SEL 133 #define CLKID_VID_PLL_IN_EN 134 #define CLKID_VID_PLL_PRE_DIV 135 #define CLKID_VID_PLL_POST_DIV 136 -#define CLKID_VID_PLL_FINAL_DIV 137 -#define CLKID_VCLK_IN_SEL 138 #define CLKID_VCLK_IN_EN 139 #define CLKID_VCLK_DIV1 140 #define CLKID_VCLK_DIV2_DIV 141 @@ -135,7 +132,6 @@ #define CLKID_VCLK_DIV6 146 #define CLKID_VCLK_DIV12_DIV 147 #define CLKID_VCLK_DIV12 148 -#define CLKID_VCLK2_IN_SEL 149 #define CLKID_VCLK2_IN_EN 150 #define CLKID_VCLK2_DIV1 151 #define CLKID_VCLK2_DIV2_DIV 152 @@ -147,17 +143,11 @@ #define CLKID_VCLK2_DIV12_DIV 158 #define CLKID_VCLK2_DIV12 159 #define CLKID_CTS_ENCT_SEL 160 -#define CLKID_CTS_ENCT 161 #define CLKID_CTS_ENCP_SEL 162 -#define CLKID_CTS_ENCP 163 #define CLKID_CTS_ENCI_SEL 164 -#define CLKID_CTS_ENCI 165 #define CLKID_HDMI_TX_PIXEL_SEL 166 -#define CLKID_HDMI_TX_PIXEL 167 #define CLKID_CTS_ENCL_SEL 168 -#define CLKID_CTS_ENCL 169 #define CLKID_CTS_VDAC0_SEL 170 -#define CLKID_CTS_VDAC0 171 #define CLKID_HDMI_SYS_SEL 172 #define CLKID_HDMI_SYS_DIV 173 #define CLKID_MALI_0_SEL 175 diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index f33781338eda..78aa07fd7cc0 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -105,6 +105,16 @@ #define CLKID_PERIPH 126 #define CLKID_AXI 128 #define CLKID_L2_DRAM 130 +#define CLKID_HDMI_PLL_HDMI_OUT 132 +#define CLKID_VID_PLL_FINAL_DIV 137 +#define CLKID_VCLK_IN_SEL 138 +#define CLKID_VCLK2_IN_SEL 149 +#define CLKID_CTS_ENCT 161 +#define CLKID_CTS_ENCP 163 +#define CLKID_CTS_ENCI 165 +#define CLKID_HDMI_TX_PIXEL 167 +#define CLKID_CTS_ENCL 169 +#define CLKID_CTS_VDAC0 171 #define CLKID_HDMI_SYS 174 #define CLKID_VPU 190 #define CLKID_VDEC_1 196