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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=E+B3m34ByFy6ScLdz0V/a8btk+7S0sAoGXDv71j9lBk=; b=jY+1Q6hD4pwVQP1vgmvytIWCYn8CjGHmIJmOWhjHHufHiC6UKnDi5HO1qO/BJhV89J Fpa2R48h88NEahUDqiF1bqthfaN80F9U2Az+0B2uw7G8LnxIiVWrUPjifmdLNzQNxJJx hqHqkghiuDtxQ65JjexpZJmPs95XTk+j9ioxGJX17ztTV4DNZ8NUJnciPo0OnbGZlIx1 iCpROeaev8ibJgffG7uRLHkJaIx7hgFji0WAhye6TW+lvraij9637CTU0PPkGuQGMS2a YnxsX52pjdKKClDkNZQfYWXakY382Iq7aN6tekXsGohz1mYsDyQ4eyhlIQiGtw8mx/PR DRdw== X-Gm-Message-State: AOAM5321Wx07O7HuVMXZfvCLUjiH6OpfPwP3jO68JgwrdBH1pC/r8sWL LjtyKVPmrXd4YnIZh0gnMVrZvIY= X-Google-Smtp-Source: ABdhPJyJbHL0WWz16f1LGpyfj+5nAJdW34N/rtHhlJdyVOFI/M3Y0N9aucxjpX7gzmgI9qVUX9/5ubM= X-Received: from pcc-desktop.svl.corp.google.com ([2620:15c:2ce:200:99b9:48f7:dbe6:8670]) (user=pcc job=sendgmr) by 2002:a5b:c0a:: with SMTP id f10mr9396108ybq.9.1626226600676; Tue, 13 Jul 2021 18:36:40 -0700 (PDT) Date: Tue, 13 Jul 2021 18:36:38 -0700 Message-Id: <20210714013638.3995315-1-pcc@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.32.0.93.g670b81a890-goog Subject: [PATCH v4] arm64: mte: optimize GCR_EL1 modification on kernel entry/exit From: Peter Collingbourne To: Catalin Marinas , Vincenzo Frascino , Will Deacon , Andrey Konovalov Cc: Peter Collingbourne , Evgenii Stepanov , Szabolcs Nagy , Tejas Belagod , linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210713_183642_490993_B8877DF1 X-CRM114-Status: GOOD ( 12.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Accessing GCR_EL1 and issuing an ISB can be expensive on some microarchitectures. Although we must write to GCR_EL1, we can restructure the code to avoid reading from it because the new value can be derived entirely from the exclusion mask, which is already in a GPR. Do so. Signed-off-by: Peter Collingbourne Link: https://linux-review.googlesource.com/id/I560a190a74176ca4cc5191dad08f77f6b1577c75 --- v4: - split in two v3: - go back to modifying on entry/exit; optimize that path instead v2: - rebase onto v9 of the tag checking mode preference series arch/arm64/kernel/entry.S | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index ce59280355c5..2d6dc62d929a 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -175,15 +175,11 @@ alternative_else_nop_endif #endif .endm - .macro mte_set_gcr, tmp, tmp2 + .macro mte_set_gcr, mte_ctrl, tmp #ifdef CONFIG_ARM64_MTE - /* - * Calculate and set the exclude mask preserving - * the RRND (bit[16]) setting. - */ - mrs_s \tmp2, SYS_GCR_EL1 - bfxil \tmp2, \tmp, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16 - msr_s SYS_GCR_EL1, \tmp2 + ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16 + orr \tmp, \tmp, #SYS_GCR_EL1_RRND + msr_s SYS_GCR_EL1, \tmp #endif .endm