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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=YOwx4SvUaJa22fnP70VgLGUe4AxJDWcKKuwZfP6ebI8=; b=NdPxYTYb+miKdVgqpsJZm7H8I3ayA8XF3h0jlsxPd+3j0gi/+cMwkDnKu1TRJyUoK5 CQTI9zYRAlkcpVRW3FyNHiUSOtfhKt/l/Zpw1qMzQnNAOJoM6kwFahDTgWCoveX1x/gO YaHdEUeXj2m/cnwwxkXi1dQz40wDFm+gVPkhHBXc2W97BJoGdMRSJRpOSjnc2UlUxwtd dOxV5ArbYhYs5v+9Ttflqd/zoyNtBO0JpFAn/BOtSrrIEGCAxwZj1Vu7McYuEVWw3MTf Jkt6iueOG+RiYT5Ew1QqfpT8YjeKvOzy1YO4d4tId9KI/bRCW2tkcV+KvRA3UMwxWgWt Ok/w== X-Gm-Message-State: AOAM5337/Ddw9CsKHWEks1v8jCZmmwF/ikTFh4lWFH4LsVWIbVbWuyxK x80CBy17/Bf6DMA+9bMSx4yvpcE= X-Google-Smtp-Source: ABdhPJxQd1wMqPoh2uWnWAd83Y1XqFzHkiaiF+YfkQq5vIlKQ49rMjgtBpJPeEcFrSpkPf9k3HWh8Ug= X-Received: from pcc-desktop.svl.corp.google.com ([2620:15c:2ce:200:99b9:48f7:dbe6:8670]) (user=pcc job=sendgmr) by 2002:a05:6214:1021:: with SMTP id k1mr8110852qvr.4.1626226876430; Tue, 13 Jul 2021 18:41:16 -0700 (PDT) Date: Tue, 13 Jul 2021 18:41:13 -0700 Message-Id: <20210714014113.4004878-1-pcc@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.32.0.93.g670b81a890-goog Subject: [PATCH v2] arm64: avoid double ISB on kernel entry From: Peter Collingbourne To: Catalin Marinas , Vincenzo Frascino , Will Deacon , Andrey Konovalov Cc: Peter Collingbourne , Evgenii Stepanov , Szabolcs Nagy , Tejas Belagod , linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210713_184118_504288_A2C87DA4 X-CRM114-Status: GOOD ( 12.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Although an ISB is required in order to make the MTE-related system register update to GCR_EL1 effective, and the same is true for PAC-related updates to SCTLR_EL1 or APIAKey{Hi,Lo}_EL1, we issue two ISBs on machines that support both features while we only need to issue one. To avoid the unnecessary additional ISB, remove the ISBs from the PAC and MTE-specific alternative blocks and add a couple of additional blocks that cause us to only execute one ISB if both features are supported. Signed-off-by: Peter Collingbourne Link: https://linux-review.googlesource.com/id/Idee7e8114d5ae5a0b171d06220a0eb4bb015a51c Acked-by: Will Deacon --- v2: - fix formatting arch/arm64/kernel/entry.S | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 2d6dc62d929a..8d63161cad8c 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -191,7 +191,6 @@ alternative_else_nop_endif ldr_l \tmp, gcr_kernel_excl mte_set_gcr \tmp, \tmp2 - isb 1: #endif .endm @@ -265,12 +264,24 @@ alternative_if ARM64_HAS_ADDRESS_AUTH orr x0, x0, SCTLR_ELx_ENIA msr sctlr_el1, x0 2: - isb alternative_else_nop_endif #endif mte_set_kernel_gcr x22, x23 + /* + * Any non-self-synchronizing system register updates required for + * kernel entry should be placed before this point. + */ +alternative_if ARM64_MTE + isb + b 1f +alternative_else_nop_endif +alternative_if ARM64_HAS_ADDRESS_AUTH + isb +alternative_else_nop_endif +1: + scs_load tsk, x20 .else add x21, sp, #PT_REGS_SIZE