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Wed, 4 Aug 2021 13:50:10 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 4 Aug 2021 13:50:09 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 4 Aug 2021 13:50:09 -0500 Received: from lelv0597.itg.ti.com (lelv0597.itg.ti.com [10.181.64.32]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 174Io9jY108085; Wed, 4 Aug 2021 13:50:09 -0500 Received: from localhost ([10.250.68.246]) by lelv0597.itg.ti.com (8.14.7/8.14.7) with ESMTP id 174Io8jL015349; Wed, 4 Aug 2021 13:50:09 -0500 From: Suman Anna To: Santosh Shilimkar , Rob Herring Subject: [PATCH v2] dt-bindings: soc: ti: pruss: Add dma-coherent property Date: Wed, 4 Aug 2021 13:50:08 -0500 Message-ID: <20210804185008.30096-1-s-anna@ti.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210804_115016_367360_41313E25 X-CRM114-Status: GOOD ( 12.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Grzegorz Jaszczyk , Grygorii Strashko , Vignesh Raghavendra , Lokesh Vutla , Kishon Vijay Abraham I , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Update the PRUSS schema file to include the dma-coherent property that indicates the coherency of the IP. The PRUSS IPs on 66AK2G SoCs do use this property. The new added dma-coherent property is a required property _only_ for 66AK2G SoCs and is not required/applicable for other SoCs, so the binding is backward compatible for other SoCs. This update is being done before the corresponding dts nodes can be added for 66AK2G SoCs. Signed-off-by: Suman Anna Reviewed-by: Grygorii Strashko Reviewed-by: Rob Herring --- v2: - No code changes, only updated the patch description (added 2nd para) to address Rob's review comments - Picked up review tags - Patch is still on top of AM64 ICSSG binding update patch [1] v1: https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20210730031901.26243-1-s-anna@ti.com/ [1] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210623165032.31223-2-s-anna@ti.com/ .../devicetree/bindings/soc/ti/ti,pruss.yaml | 37 +++++++++++++------ 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml index 47d7fd24bc56..9d128b9e7deb 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml @@ -85,6 +85,8 @@ properties: dma-ranges: maxItems: 1 + dma-coherent: true + power-domains: description: | This property is as per sci-pm-domain.txt. @@ -324,18 +326,29 @@ additionalProperties: false # - interrupt-controller # - pru -if: - properties: - compatible: - contains: - enum: - - ti,k2g-pruss - - ti,am654-icssg - - ti,j721e-icssg - - ti,am642-icssg -then: - required: - - power-domains +allOf: + - if: + properties: + compatible: + contains: + enum: + - ti,k2g-pruss + - ti,am654-icssg + - ti,j721e-icssg + - ti,am642-icssg + then: + required: + - power-domains + + - if: + properties: + compatible: + contains: + enum: + - ti,k2g-pruss + then: + required: + - dma-coherent examples: - |